URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Diff between revs 76 and 78

Rev 76	Rev 78
Line 92...	Line 92...
`fake_mem[16] = STA_ABS; // testing ABS mode, WRITE type. should write alu_result on MEM[1]`	`fake_mem[16] = STA_ABS; // testing ABS mode, WRITE type. should write alu_result on MEM[1]`
`fake_mem[17] = 8'h01;`	`fake_mem[17] = 8'h01;`
`fake_mem[18] = 8'h00;`	`fake_mem[18] = 8'h00;`
`fake_mem[19] = LDA_ZPG; // testing ZPG mode, READ type`	`fake_mem[19] = LDA_ZPG; // testing ZPG mode, READ type`
`fake_mem[20] = 8'h00;`	`fake_mem[20] = 8'h00;`
`fake_mem[21] = 8'h00;`	`fake_mem[21] = ASL_ZPG; // testing ZPG mode, READ_MODIFY_WRITE type`
	`fake_mem[22] = 8'h00;`
	`fake_mem[23] = STA_ZPG; // testing ZPG mode, WRITE type`
	`fake_mem[24] = 8'h00;`

`@(negedge clk) // will wait for next negative edge of the clock (t=20)`	`@(negedge clk) // will wait for next negative edge of the clock (t=20)`
`reset_n=1'b1;`	`reset_n=1'b1;`


`#700;`	`#1000;`
`$finish; // to shut down the simulation`	`$finish; // to shut down the simulation`
`end //initial`	`end //initial`

`always @(clk) begin`	`always @(clk) begin`
`if (control == 0) begin // MEM_READ`	`if (control == 0) begin // MEM_READ`