URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Diff between revs 86 and 87

Rev 86	Rev 87
Line 107...	Line 107...
`fake_mem[26] = 8'h01;`	`fake_mem[26] = 8'h01;`
`fake_mem[27] = ASL_ZPX; // testing ZPX mode, READ_MODIFY_WRITE type. MEM[x+1] = MEM[x+1] << 1;`	`fake_mem[27] = ASL_ZPX; // testing ZPX mode, READ_MODIFY_WRITE type. MEM[x+1] = MEM[x+1] << 1;`
`fake_mem[28] = 8'h01;`	`fake_mem[28] = 8'h01;`
`fake_mem[29] = STA_ZPX; // testing ZPX mode, WRITE type. MEM[x+2] = A;`	`fake_mem[29] = STA_ZPX; // testing ZPX mode, WRITE type. MEM[x+2] = A;`
`fake_mem[30] = 8'h02;`	`fake_mem[30] = 8'h02;`
	`fake_mem[31] = LDA_ABX; // testing ABX mode, READ TYPE. No page crossed.`
	`fake_mem[32] = 8'h0a;`
	`fake_mem[33] = 8'h00;`


`@(negedge clk) // will wait for next negative edge of the clock (t=20)`	`@(negedge clk) // will wait for next negative edge of the clock (t=20)`
`reset_n=1'b1;`	`reset_n=1'b1;`


`#1000;`	`#2000;`
`$finish; // to shut down the simulation`	`$finish; // to shut down the simulation`
`end //initial`	`end //initial`

`always @(clk) begin`	`always @(clk) begin`
`if (control == 0) begin // MEM_READ`	`if (control == 0) begin // MEM_READ`