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https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Diff between revs 87 and 88
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| Rev 87 |
Rev 88 |
| Line 110... |
Line 110... |
fake_mem[29] = STA_ZPX; // testing ZPX mode, WRITE type. MEM[x+2] = A;
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fake_mem[29] = STA_ZPX; // testing ZPX mode, WRITE type. MEM[x+2] = A;
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fake_mem[30] = 8'h02;
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fake_mem[30] = 8'h02;
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fake_mem[31] = LDA_ABX; // testing ABX mode, READ TYPE. No page crossed.
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fake_mem[31] = LDA_ABX; // testing ABX mode, READ TYPE. No page crossed.
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fake_mem[32] = 8'h0a;
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fake_mem[32] = 8'h0a;
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fake_mem[33] = 8'h00;
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fake_mem[33] = 8'h00;
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fake_mem[34] = LDA_ABX; // testing ABX mode, READ TYPE. Page crossed.
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fake_mem[35] = 8'hff;
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fake_mem[36] = 8'h00;
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@(negedge clk) // will wait for next negative edge of the clock (t=20)
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@(negedge clk) // will wait for next negative edge of the clock (t=20)
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reset_n=1'b1;
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reset_n=1'b1;
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