URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Diff between revs 88 and 89

Rev 88	Rev 89
Line 66...	Line 66...

`t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);`	`t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);`

`always #10 clk = ~clk;`	`always #10 clk = ~clk;`

`reg[7:0] fake_mem[40:0];`	`reg[7:0] fake_mem[100:0];`

`initial begin`	`initial begin`
`clk = 0;`	`clk = 0;`
`reset_n = 1'b0;`	`reset_n = 1'b0;`
`alu_result = 8'h01;`	`alu_result = 8'h01;`
Line 113...	Line 113...
`fake_mem[32] = 8'h0a;`	`fake_mem[32] = 8'h0a;`
`fake_mem[33] = 8'h00;`	`fake_mem[33] = 8'h00;`
`fake_mem[34] = LDA_ABX; // testing ABX mode, READ TYPE. Page crossed.`	`fake_mem[34] = LDA_ABX; // testing ABX mode, READ TYPE. Page crossed.`
`fake_mem[35] = 8'hff;`	`fake_mem[35] = 8'hff;`
`fake_mem[36] = 8'h00;`	`fake_mem[36] = 8'h00;`
	`fake_mem[37] = ASL_ABX; // testing ABX mode, READ_MODIFY_WRITE TYPE. No page crossed.`
	`fake_mem[38] = 8'h01;`
	`fake_mem[39] = 8'h00;`


`@(negedge clk) // will wait for next negative edge of the clock (t=20)`	`@(negedge clk) // will wait for next negative edge of the clock (t=20)`
`reset_n=1'b1;`	`reset_n=1'b1;`