URL
https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Diff between revs 91 and 92
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 91 |
Rev 92 |
| Line 119... |
Line 119... |
fake_mem[38] = 8'h01;
|
fake_mem[38] = 8'h01;
|
fake_mem[39] = 8'h00;
|
fake_mem[39] = 8'h00;
|
fake_mem[40] = ASL_ABX; // testing ABX mode, READ_MODIFY_WRITE TYPE. Page crossed.
|
fake_mem[40] = ASL_ABX; // testing ABX mode, READ_MODIFY_WRITE TYPE. Page crossed.
|
fake_mem[41] = 8'hff;
|
fake_mem[41] = 8'hff;
|
fake_mem[42] = 8'h00;
|
fake_mem[42] = 8'h00;
|
|
fake_mem[40] = STA_ABX; // testing ABX mode, WRITE TYPE. No page crossed.
|
|
fake_mem[41] = 8'h04;
|
|
fake_mem[42] = 8'h00;
|
|
|
|
|
@(negedge clk) // will wait for next negative edge of the clock (t=20)
|
@(negedge clk) // will wait for next negative edge of the clock (t=20)
|
reset_n=1'b1;
|
reset_n=1'b1;
|
|
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
