| Line 60... |
Line 60... |
wire [7:0] data_out;
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wire [7:0] data_out;
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wire [7:0] alu_opcode;
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wire [7:0] alu_opcode;
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wire [7:0] alu_a;
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wire [7:0] alu_a;
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wire alu_enable;
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wire alu_enable;
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integer i;
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`include "../T6507LP_Package.v"
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`include "../T6507LP_Package.v"
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t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);
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t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);
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always #10 clk = ~clk;
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always #10 clk = ~clk;
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reg[7:0] fake_mem[2000:0];
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reg[7:0] fake_mem[2**13-1:0];
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initial begin
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initial begin
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clk = 0;
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clk = 0;
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reset_n = 1'b0;
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reset_n = 1'b0;
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alu_result = 8'h01;
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alu_result = 8'h01;
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alu_status = 8'h00;
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alu_status = 8'h00;
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alu_x = 8'h07;
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alu_x = 8'h07;
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alu_y = 8'h03;
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alu_y = 8'h03;
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for (i=0; i < 2**13; i= i+1) begin
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$write("\n%d",i);
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fake_mem[i]=8'h00;
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end
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fake_mem[0] = ASL_ACC; // testing ACC mode
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fake_mem[0] = ASL_ACC; // testing ACC mode
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fake_mem[1] = ADC_IMM; // testing IMM mode
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fake_mem[1] = ADC_IMM; // testing IMM mode
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fake_mem[2] = 8'h27;
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fake_mem[2] = 8'h27;
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fake_mem[3] = JMP_ABS; // testing ABS mode, JMP type
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fake_mem[3] = JMP_ABS; // testing ABS mode, JMP type
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fake_mem[4] = 8'h09;
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fake_mem[4] = 8'h09;
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| Line 132... |
Line 140... |
fake_mem[58] = BNE_REL; // testing REL mode, taking a branch, page crossed.
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fake_mem[58] = BNE_REL; // testing REL mode, taking a branch, page crossed.
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fake_mem[59] = 8'hff;
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fake_mem[59] = 8'hff;
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fake_mem[315] = BEQ_REL; // testing REL mode, not taking a branch, page would have crossed.
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fake_mem[315] = BEQ_REL; // testing REL mode, not taking a branch, page would have crossed.
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fake_mem[316] = 8'hff;
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fake_mem[316] = 8'hff;
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fake_mem[317] = BEQ_REL; // testing REL mode, not taking a branch, page would not have crossed.
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fake_mem[317] = BEQ_REL; // testing REL mode, not taking a branch, page would not have crossed.
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fake_mem[318] = 8'h0;
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fake_mem[318] = 8'h00;
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fake_mem[319] = LDA_IDX; // testing IDX mode READ TYPE, no page crossed;
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fake_mem[320] = 8'h0a;
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fake_mem[321] = LDA_IDX; // testing IDX mode READ TYPE, page crossed; this will actually do A = MEM[6] because there is no carry
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fake_mem[322] = 8'hff;
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//fake_mem[319] = SLO_IDX; // testing IDX mode READ_MODIFY_WRITE TYPE
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//fake_mem[320] = 8'h0a; // all of read modify write instructions are not documented therefore will not be simulated
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fake_mem[323] = STA_IDX; // testing IDX mode WRITE TYPE, page crossed being ignored
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fake_mem[324] = 8'hff;
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fake_mem[325] = STA_IDX; // testing IDX mode WRITE TYPE, page not crossed;
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fake_mem[326] = 8'hff;
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//fake_mem[321] = LDA_IDX; // testing IDX mode READ TYPE, page crossed;
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//fake_mem[322] = 8'hff;
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@(negedge clk) // will wait for next negative edge of the clock (t=20)
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@(negedge clk) // will wait for next negative edge of the clock (t=20)
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reset_n=1'b1;
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reset_n=1'b1;
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#2000;
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#3000;
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$finish; // to shut down the simulation
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$finish; // to shut down the simulation
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end //initial
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end //initial
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always @(clk) begin
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always @(clk) begin
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if (control == 0) begin // MEM_READ
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if (control == 0) begin // MEM_READ
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