OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Diff between revs 95 and 96

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 95 Rev 96
Line 123... Line 123...
                fake_mem[34] = LDA_ABX; // testing ABX mode, READ TYPE. Page crossed.
                fake_mem[34] = LDA_ABX; // testing ABX mode, READ TYPE. Page crossed.
                fake_mem[35] = 8'hff;
                fake_mem[35] = 8'hff;
                fake_mem[36] = 8'h00;
                fake_mem[36] = 8'h00;
                fake_mem[37] = ASL_ABX; // testing ABX mode, READ_MODIFY_WRITE TYPE. No page crossed.
                fake_mem[37] = ASL_ABX; // testing ABX mode, READ_MODIFY_WRITE TYPE. No page crossed.
                fake_mem[38] = 8'h01;
                fake_mem[38] = 8'h01;
                fake_mem[39] = 8'h00;
                fake_mem[39] = 8'd35;
                fake_mem[40] = ASL_ABX; // testing ABX mode, READ_MODIFY_WRITE TYPE. Page crossed.
                fake_mem[40] = ASL_ABX; // testing ABX mode, READ_MODIFY_WRITE TYPE. Page crossed.
                fake_mem[41] = 8'hff;
                fake_mem[41] = 8'hff;
                fake_mem[42] = 8'h00;
                fake_mem[42] = 8'h00;
                fake_mem[40] = STA_ABX; // testing ABX mode, WRITE TYPE. No page crossed.
                fake_mem[40] = STA_ABX; // testing ABX mode, WRITE TYPE. No page crossed.
                fake_mem[41] = 8'h04;
                fake_mem[41] = 8'h04;
Line 137... Line 137...
                fake_mem[45] = 8'h00;
                fake_mem[45] = 8'h00;
                fake_mem[46] = BNE_REL; // testing REL mode, taking a branch, no page crossed.
                fake_mem[46] = BNE_REL; // testing REL mode, taking a branch, no page crossed.
                fake_mem[47] = 8'h0a;
                fake_mem[47] = 8'h0a;
                fake_mem[58] = BNE_REL; // testing REL mode, taking a branch, page crossed.
                fake_mem[58] = BNE_REL; // testing REL mode, taking a branch, page crossed.
                fake_mem[59] = 8'hff;
                fake_mem[59] = 8'hff;
 
                fake_mem[254] = 8'hff;
 
                fake_mem[255] = 8'h11;
                fake_mem[315] = BEQ_REL; // testing REL mode, not taking a branch, page would have crossed.
                fake_mem[315] = BEQ_REL; // testing REL mode, not taking a branch, page would have crossed.
                fake_mem[316] = 8'hff;
                fake_mem[316] = 8'hff;
                fake_mem[317] = BEQ_REL; // testing REL mode, not taking a branch, page would not have crossed.
                fake_mem[317] = BEQ_REL; // testing REL mode, not taking a branch, page would not have crossed.
                fake_mem[318] = 8'h00;
                fake_mem[318] = 8'h00;
                fake_mem[319] = LDA_IDX; // testing IDX mode READ TYPE, no page crossed;
                fake_mem[319] = LDA_IDX; // testing IDX mode READ TYPE, no page crossed;
Line 150... Line 152...
                //fake_mem[319] = SLO_IDX; // testing IDX mode READ_MODIFY_WRITE TYPE
                //fake_mem[319] = SLO_IDX; // testing IDX mode READ_MODIFY_WRITE TYPE
                //fake_mem[320] = 8'h0a;   // all of read modify write instructions are not documented therefore will not be simulated
                //fake_mem[320] = 8'h0a;   // all of read modify write instructions are not documented therefore will not be simulated
                fake_mem[323] = STA_IDX; // testing IDX mode WRITE TYPE, page crossed being ignored
                fake_mem[323] = STA_IDX; // testing IDX mode WRITE TYPE, page crossed being ignored
                fake_mem[324] = 8'hff;
                fake_mem[324] = 8'hff;
                fake_mem[325] = STA_IDX; // testing IDX mode WRITE TYPE, page not crossed;
                fake_mem[325] = STA_IDX; // testing IDX mode WRITE TYPE, page not crossed;
                fake_mem[326] = 8'hff;
                fake_mem[326] = 8'h00;
                //fake_mem[321] = LDA_IDX; // testing IDX mode READ TYPE, page crossed;
                fake_mem[327] = LDA_IDY; // testing IDY mode READ TYPE, page not crossed;
                //fake_mem[322] = 8'hff;        
                fake_mem[328] = 8'h00;
 
                fake_mem[329] = LDA_IDY; // testing IDY mode READ TYPE, page not crossed but pointer overflowed.
 
                fake_mem[330] = 8'hff;
 
                /* testing IDY mode READ TYPE, page crossed.
 
                   address may assume a invalid value when page is crossed but it is fixed on the next cycle when the true read occurs.
 
                   this is probably not an issue */
 
                fake_mem[331] = LDA_IDY;
 
                fake_mem[332] = 8'hfe;
 
// FALTOU O WRITE INDIRETO Y!
                @(negedge clk) // will wait for next negative edge of the clock (t=20)
                @(negedge clk) // will wait for next negative edge of the clock (t=20)
                reset_n=1'b1;
                reset_n=1'b1;
 
 
 
 
                #3000;
                #3000;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.