OpenCores

Rev 96	Rev 98
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`//// ////`	`//// ////`
`//// This file is part of the T6507LP project ////`	`//// This file is part of the T6507LP project ////`
`//// http://www.opencores.org/cores/t6507lp/ ////`	`//// http://www.opencores.org/cores/t6507lp/ ////`
`//// ////`	`//// ////`
`//// Description ////`	`//// Description ////`
`//// 6507 FSM ////`	`//// 6507 FSM testbench ////`
`//// ////`	`//// ////`
`//// TODO: ////`	`//// TODO: ////`
`//// - Perform simple tests before going into serious verification ////`	`//// - Test indirect indexed mode ////`
	`//// - Test absolute indirect mode ////`
	`//// - Test special stack instructions ////`
`//// ////`	`//// ////`
`//// Author(s): ////`	`//// Author(s): ////`
`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`	`//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////`
`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`	`//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////`
`//// ////`	`//// ////`
Line 54...	Line 56...

`reg [7:0] alu_x;`	`reg [7:0] alu_x;`
`reg [7:0] alu_y;`	`reg [7:0] alu_y;`

`wire [12:0] address;`	`wire [12:0] address;`
`wire control; // one bit is enough? read = 0, write = 1`	`wire control;`
`wire [7:0] data_out;`	`wire [7:0] data_out;`
`wire [7:0] alu_opcode;`	`wire [7:0] alu_opcode;`
`wire [7:0] alu_a;`	`wire [7:0] alu_a;`
`wire alu_enable;`	`wire alu_enable;`

`integer i;`	`integer i;`

`include "../T6507LP_Package.v"	`include "../T6507LP_Package.v" // TODO: remove this include

`t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);`	`t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);`

`always #10 clk = ~clk;`	`always #10 clk = ~clk;`

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////                                                                    ////

////                                                                    ////

//// This file is part of the T6507LP project                           ////

//// This file is part of the T6507LP project                           ////

//// http://www.opencores.org/cores/t6507lp/                            ////

//// http://www.opencores.org/cores/t6507lp/                            ////

////                                                                    ////

////                                                                    ////

//// Description                                                        ////

//// Description                                                        ////

//// 6507 FSM                                                           ////

//// 6507 FSM testbench                                                 ////

////                                                                    ////

////                                                                    ////

//// TODO:                                                              ////

//// TODO:                                                              ////

//// - Perform simple tests before going into serious verification      ////

//// - Test indirect indexed mode                                       ////

//// - Test absolute indirect mode                                      ////

//// - Test special stack instructions                                  ////

////                                                                    ////

////                                                                    ////

//// Author(s):                                                         ////

//// Author(s):                                                         ////

//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////

//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com                    ////

//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////

//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com     ////

////                                                                    ////

////                                                                    ////

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        reg [7:0] alu_x;

        reg [7:0] alu_x;

        reg [7:0] alu_y;

        reg [7:0] alu_y;

        wire [12:0] address;

        wire [12:0] address;

        wire control; // one bit is enough? read = 0, write = 1

        wire control;

        wire [7:0] data_out;

        wire [7:0] data_out;

        wire [7:0] alu_opcode;

        wire [7:0] alu_opcode;

        wire [7:0] alu_a;

        wire [7:0] alu_a;

        wire alu_enable;

        wire alu_enable;

        integer i;

        integer i;

        `include "../T6507LP_Package.v"

        `include "../T6507LP_Package.v" // TODO: remove this include

        t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);

        t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);

        always #10 clk = ~clk;

        always #10 clk = ~clk;

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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Diff between revs 96 and 98