| Line 56... |
Line 56... |
input enable;
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input enable;
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input rw_mem;
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input rw_mem;
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input [ADDR_SIZE_:0] address;
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input [ADDR_SIZE_:0] address;
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inout [DATA_SIZE_:0] data;
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inout [DATA_SIZE_:0] data;
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wire [DATA_SIZE_:0] ram [127:0];
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reg [DATA_SIZE_:0] ram [127:0];
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wire [DATA_SIZE_:0] io_ports [3:0]; // porta, portaddr, portb, portbddr
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reg [DATA_SIZE_:0] port_a;
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reg [DATA_SIZE_:0] port_b;
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reg [DATA_SIZE_:0] ddra;
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wire [DATA_SIZE_:0] ddrb;
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reg [DATA_SIZE_:0] data_drv;
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reg [DATA_SIZE_:0] data_drv;
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assign data = (rw_mem) ? 8'bZ: data_drv; // if i am writing the bus receives the data from cpu
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assign data = (rw_mem) ? 8'bZ: data_drv; // if i am writing the bus receives the data from cpu, else local data.
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t6532_io t6532_io (
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.clk (clk),
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.io_lines (io_lines),
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.ddra (io_ports[1]),
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.A (io_ports[0]),
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.B (io_ports[2])
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);
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always @(clk) begin
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always @(clk) begin
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port_b[0] <= ~io_lines[0]; // these two are not actually switches
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port_b[1] <= ~io_lines[1];
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if (io_lines[3]) begin // these are.
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port_b[3] <= !port_b[3];
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end
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if (io_lines[6]) begin
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port_b[6] <= !port_b[6];
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end
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if (io_lines[7]) begin
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port_b[7] <= !port_b[7];
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end
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port_a[0] <= (ddra[0] == 0) ? io_lines[8] : port_a[0];
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port_a[1] <= (ddra[1] == 0) ? io_lines[9] : port_a[1];
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port_a[2] <= (ddra[2] == 0) ? io_lines[10] : port_a[2];
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port_a[3] <= (ddra[3] == 0) ? io_lines[11] : port_a[3];
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port_a[4] <= (ddra[4] == 0) ? io_lines[12] : port_a[4];
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port_a[5] <= (ddra[5] == 0) ? io_lines[13] : port_a[5];
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port_a[6] <= (ddra[6] == 0) ? io_lines[14] : port_a[6];
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port_a[7] <= (ddra[7] == 0) ? io_lines[15] : port_a[7];
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if (enable && rw_mem) begin
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if (enable && rw_mem) begin
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case (address)
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case (address)
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8'h80: data_drv <= io_ports[0];
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8'h80: data_drv = port_a;
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8'h81: data_drv = ddra;
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8'h82: data_drv = port_b;
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8'h83: data_drv = ddrb;
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8'h84: ;
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8'h94: ;
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8'h95: ;
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8'h96: ;
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8'h97: ;
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default: ;
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default: ;
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endcase
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endcase
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end
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end
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end
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end
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always @(*) begin
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always @(*) begin
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io_ports [3] = 8'h00; // portb ddr is always input
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io_ports [3] = 8'h00; // portb ddr is always input
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io_ports[1] = ddra;
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end
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end
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// io
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// io
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// timer
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// timer
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// ram
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// ram
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