| Line 60... |
Line 60... |
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reg [DATA_SIZE_:0] ram [127:0];
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reg [DATA_SIZE_:0] ram [127:0];
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reg [DATA_SIZE_:0] port_a;
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reg [DATA_SIZE_:0] port_a;
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reg [DATA_SIZE_:0] port_b;
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reg [DATA_SIZE_:0] port_b;
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reg [DATA_SIZE_:0] ddra;
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reg [DATA_SIZE_:0] ddra;
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wire [DATA_SIZE_:0] ddrb;
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reg [DATA_SIZE_:0] timer;
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reg [DATA_SIZE_:0] 1c_timer;
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reg [DATA_SIZE_:0] 8c_timer;
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reg [DATA_SIZE_:0] 64c_timer;
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reg [DATA_SIZE_:0] 1024c_timer;
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reg [DATA_SIZE_:0] data_drv;
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reg [DATA_SIZE_:0] data_drv;
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assign data = (rw_mem) ? 8'bZ: data_drv; // if i am writing the bus receives the data from cpu, else local data.
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assign data = (rw_mem) ? 8'bZ: data_drv; // if i am writing the bus receives the data from cpu, else local data.
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| Line 89... |
Line 93... |
port_a[4] <= (ddra[4] == 0) ? io_lines[12] : port_a[4];
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port_a[4] <= (ddra[4] == 0) ? io_lines[12] : port_a[4];
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port_a[5] <= (ddra[5] == 0) ? io_lines[13] : port_a[5];
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port_a[5] <= (ddra[5] == 0) ? io_lines[13] : port_a[5];
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port_a[6] <= (ddra[6] == 0) ? io_lines[14] : port_a[6];
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port_a[6] <= (ddra[6] == 0) ? io_lines[14] : port_a[6];
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port_a[7] <= (ddra[7] == 0) ? io_lines[15] : port_a[7];
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port_a[7] <= (ddra[7] == 0) ? io_lines[15] : port_a[7];
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if (enable && rw_mem) begin
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if (enable && rw_mem == 0) begin // reading!
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case (address)
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case (address)
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8'h80: data_drv = port_a;
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8'h80: data_drv = port_a;
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8'h81: data_drv = ddra;
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8'h81: data_drv = ddra;
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8'h82: data_drv = port_b;
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8'h82: data_drv = port_b;
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8'h83: data_drv = ddrb;
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8'h83: data_drv = 8'h00; // portb ddr is always input
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8'h84: ;
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8'h84: data_drv = timer;
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8'h94: ;
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8'h94: ;
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8'h95: ;
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8'h95: ;
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8'h96: ;
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8'h96: ;
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8'h97: ;
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8'h97: ;
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default: ;
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default: ;
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endcase
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endcase
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end
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end
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end
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end
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always @(*) begin
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io_ports[3] = 8'h00; // portb ddr is always input
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io_ports[1] = ddra;
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end
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// io
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// timer
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// timer
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// ram
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// ram
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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