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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module t6532(clk, io_lines, enable, rw_mem, address, data);
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module t6532(clk, reset_n, io_lines, enable, rw_mem, address, data);
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] ADDR_SIZE = 4'd7; // this is the *local* addr_size
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parameter [3:0] ADDR_SIZE = 4'd10; // this is the *local* addr_size
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
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localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
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localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
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input clk; // master clock signal, 1.19mhz
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input clk; // master clock signal, 1.19mhz
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input reset_n;
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input [15:0] io_lines; // inputs from the keyboard controller
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input [15:0] io_lines; // inputs from the keyboard controller
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input enable; // since the address bus is shared an enable signal is used
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input enable; // since the address bus is shared an enable signal is used
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input rw_mem; // read == 0, write == 1
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input rw_mem; // read == 0, write == 1
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input [ADDR_SIZE_:0] address; // system address bus
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input [ADDR_SIZE_:0] address; // system address bus
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inout [DATA_SIZE_:0] data; // controler <=> riot data bus
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inout [DATA_SIZE_:0] data; // controler <=> riot data bus
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reg [DATA_SIZE_:0] ram [8'h80:8'hFF]; // the ram itself. TODO: test the memory compiler
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reg [DATA_SIZE_:0] ram [8'hFF:8'h80]; // the ram itself. TODO: test the memory compiler
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reg [DATA_SIZE_:0] port_a;
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reg [DATA_SIZE_:0] port_a;
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reg [DATA_SIZE_:0] port_b;
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reg [DATA_SIZE_:0] port_b;
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reg [DATA_SIZE_:0] ddra;
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reg [DATA_SIZE_:0] ddra;
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reg [DATA_SIZE_:0] timer; // the timer
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reg [DATA_SIZE_:0] timer; // the timer
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reg c1_timer; // 1 clock cycle counter enable
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reg c1_timer; // 1 clock cycle counter enable
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reg writing;
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reg writing;
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reg writing_at_timer;
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reg writing_at_timer;
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reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus
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reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus
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assign data = (rw_mem) ? 8'bZ: data_drv; // if under writing the bus receives the data from cpu, else local data.
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assign data = (rw_mem || !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data.
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always @(posedge clk) begin // I/O handling
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always @(posedge clk or negedge reset_n) begin // I/O handling
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if (reset_n == 1'b0) begin
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port_a <= 8'h00;
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port_b <= 8'h00;
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ddra <= 8'h00;
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end
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else begin
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port_b[0] <= ~io_lines[0]; // these two are not actually switches
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port_b[0] <= ~io_lines[0]; // these two are not actually switches
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port_b[1] <= ~io_lines[1];
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port_b[1] <= ~io_lines[1];
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if (io_lines[3]) begin // these are.
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if (io_lines[3]) begin // these are.
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port_b[3] <= !port_b[3];
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port_b[3] <= !port_b[3];
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end
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end
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if (io_lines[7]) begin
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if (io_lines[7]) begin
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port_b[7] <= !port_b[7];
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port_b[7] <= !port_b[7];
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end
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end
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port_a[0] <= (ddra[0] == 0) ? io_lines[8] : port_a[0];
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port_a[0] <= (ddra[0] == 1'b0) ? io_lines[8] : port_a[0];
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port_a[1] <= (ddra[1] == 0) ? io_lines[9] : port_a[1];
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port_a[1] <= (ddra[1] == 1'b0) ? io_lines[9] : port_a[1];
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port_a[2] <= (ddra[2] == 0) ? io_lines[10] : port_a[2];
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port_a[2] <= (ddra[2] == 1'b0) ? io_lines[10] : port_a[2];
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port_a[3] <= (ddra[3] == 0) ? io_lines[11] : port_a[3];
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port_a[3] <= (ddra[3] == 1'b0) ? io_lines[11] : port_a[3];
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port_a[4] <= (ddra[4] == 0) ? io_lines[12] : port_a[4];
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port_a[4] <= (ddra[4] == 1'b0) ? io_lines[12] : port_a[4];
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port_a[5] <= (ddra[5] == 0) ? io_lines[13] : port_a[5];
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port_a[5] <= (ddra[5] == 1'b0) ? io_lines[13] : port_a[5];
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port_a[6] <= (ddra[6] == 0) ? io_lines[14] : port_a[6];
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port_a[6] <= (ddra[6] == 1'b0) ? io_lines[14] : port_a[6];
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port_a[7] <= (ddra[7] == 0) ? io_lines[15] : port_a[7];
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port_a[7] <= (ddra[7] == 1'b0) ? io_lines[15] : port_a[7];
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end
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end
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end
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always @(posedge clk) begin // R/W register/memory handling
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always @(posedge clk or negedge reset_n) begin // R/W register/memory handling
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if (reset_n == 1'b0) begin
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data_drv <= 8'h00;
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c1_timer <= 1'b0;
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c8_timer <= 1'b0;
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c64_timer <= 1'b0;
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c1024_timer <= 1'b0;
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timer <= 8'h00;
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flipped <= 1'b0;
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counter <= 11'd0;
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end
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else begin
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if (reading) begin // reading!
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if (reading) begin // reading!
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case (address)
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case (address)
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10'h280: data_drv <= port_a;
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10'h280: data_drv <= port_a;
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10'h281: data_drv <= ddra;
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10'h281: data_drv <= ddra;
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10'h282: data_drv <= port_b;
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10'h282: data_drv <= port_b;
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10'h283: data_drv <= 8'h00; // portb ddr is always input
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10'h283: data_drv <= 8'h00; // portb ddr is always input
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10'h284: data_drv <= timer;
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10'h284: data_drv <= timer;
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default: data_drv <= ram[address];
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default: data_drv <= ram[address[6:0]];
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endcase
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endcase
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end
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end
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else if (writing) begin // writing!
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else if (writing) begin // writing!
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case (address)
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case (address)
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10'h294: begin
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10'h294: begin
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c1_timer <= 1;
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c1_timer <= 1'b1;
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c8_timer <= 0;
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c8_timer <= 1'b0;
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c64_timer <= 0;
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c64_timer <= 1'b0;
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c1024_timer <= 0;
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c1024_timer <= 1'b0;
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timer <= data;
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timer <= data;
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flipped <= 0;
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flipped <= 1'b0;
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counter <= 1;
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counter <= 11'd1;
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end
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end
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10'h295: begin
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10'h295: begin
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c1_timer <= 0;
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c1_timer <= 1'b0;
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c8_timer <= 1;
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c8_timer <= 1'b1;
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c64_timer <= 0;
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c64_timer <= 1'b0;
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c1024_timer <= 0;
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c1024_timer <= 1'b0;
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timer <= data;
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timer <= data;
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flipped <= 0;
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flipped <= 1'b0;
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counter <= 8;
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counter <= 11'd8;
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end
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end
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10'h296: begin
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10'h296: begin
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c1_timer <= 0;
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c1_timer <= 1'b0;
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c8_timer <= 0;
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c8_timer <= 1'b0;
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c64_timer <= 1;
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c64_timer <= 1'b1;
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c1024_timer <= 0;
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c1024_timer <= 1'b0;
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timer <= data;
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timer <= data;
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flipped <= 0;
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flipped <= 1'b0;
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counter <= 64;
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counter <= 11'd64;
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end
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end
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10'h297: begin
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10'h297: begin
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c1_timer <= 0;
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c1_timer <= 1'b0;
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c8_timer <= 0;
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c8_timer <= 1'b0;
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c64_timer <= 0;
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c64_timer <= 1'b0;
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c1024_timer <= 1;
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c1024_timer <= 1'b1;
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timer <= data;
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timer <= data;
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flipped <= 0;
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flipped <= 1'b0;
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counter <= 1024;
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counter <= 11'd1024;
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end
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end
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default: begin
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default: begin
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ram[address] <= data;
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ram[address[6:0]] <= data;
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end
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end
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endcase
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endcase
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end
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end
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end
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always @(posedge clk) begin // timer!
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if (!writing_at_timer) begin
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if (!writing_at_timer) begin
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if (counter == 0) begin
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if (counter == 11'd0) begin
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timer <= timer - 1;
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timer <= timer - 8'd1;
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if (timer == 0) begin
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if (timer == 8'd0) begin
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flipped <= 1'b1;
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flipped <= 1'b1;
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end
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end
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if (c1_timer || flipped) begin
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if (c1_timer || flipped) begin
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counter <= 1;
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counter <= 11'd1;
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end
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end
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if (c8_timer) begin
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if (c8_timer) begin
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counter <= 8;
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counter <= 11'd8;
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end
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end
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if (c64_timer) begin
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if (c64_timer) begin
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counter <= 64;
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counter <= 11'd64;
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end
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end
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if (c1024_timer) begin
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if (c1024_timer) begin
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counter <= 1024;
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counter <= 11'd1024;
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end
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end
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end
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end
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else begin
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else begin
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counter <= counter - 1;
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counter <= counter - 11'd1;
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end
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end
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end
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end
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end
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end
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end
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always @(*) begin// logic for easier controlling
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always @(*) begin// logic for easier controlling
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reading = 1'b0;
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reading = 1'b0;
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writing = 1'b0;
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writing = 1'b0;
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writing_at_timer = 1'b0;
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writing_at_timer = 1'b0;
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if (enable && rw_mem == 0) begin
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if (enable && reset_n) begin
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if (rw_mem == 1'b0) begin
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reading = 1'b1;
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reading = 1'b1;
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end
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end
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else if (enable && rw_mem) begin
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else begin
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writing = 1'b1;
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writing = 1'b1;
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if (address == 10'h294 || address == 10'h295 || address == 10'h296 || address == 10'h297) begin
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if ( (address == 10'h294) || (address == 10'h295) || (address == 10'h296) || (address == 10'h297) ) begin
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writing_at_timer = 1'b1;
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writing_at_timer = 1'b1;
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end
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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