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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module t6532(clk, reset_n, io_lines, enable, rw_mem, address, data);
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module t6532(clk, reset_n, io_lines, enable, mem_rw, address, data);
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] ADDR_SIZE = 4'd10; // this is the *local* addr_size
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parameter [3:0] ADDR_SIZE = 4'd10; // this is the *local* addr_size
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
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localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
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localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
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input clk; // master clock signal, 1.19mhz
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input clk; // master clock signal, 1.19mhz
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input reset_n;
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input reset_n;
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input [15:0] io_lines; // inputs from the keyboard controller
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input [15:0] io_lines; // inputs from the keyboard controller
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input enable; // since the address bus is shared an enable signal is used
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input enable; // since the address bus is shared an enable signal is used
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input rw_mem; // read == 0, write == 1
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input mem_rw; // read == 0, write == 1
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input [ADDR_SIZE_:0] address; // system address bus
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input [ADDR_SIZE_:0] address; // system address bus
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inout [DATA_SIZE_:0] data; // controler <=> riot data bus
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inout [DATA_SIZE_:0] data; // controler <=> riot data bus
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reg [DATA_SIZE_:0] ram [8'hFF:8'h80]; // the ram itself. TODO: test the memory compiler
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reg [DATA_SIZE_:0] ram [8'hFF:8'h80]; // the ram itself. TODO: test the memory compiler
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reg [DATA_SIZE_:0] port_a;
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reg [DATA_SIZE_:0] port_a;
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reg writing;
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reg writing;
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reg writing_at_timer;
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reg writing_at_timer;
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reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus
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reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus
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assign data = (rw_mem || !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data.
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assign data = (mem_rw || !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data.
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always @(posedge clk or negedge reset_n) begin // I/O handling
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always @(posedge clk or negedge reset_n) begin // I/O handling
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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port_a <= 8'h00;
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port_a <= 8'h00;
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port_b <= 8'h00;
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port_b <= 8'h00;
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reading = 1'b0;
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reading = 1'b0;
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writing = 1'b0;
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writing = 1'b0;
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writing_at_timer = 1'b0;
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writing_at_timer = 1'b0;
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if (enable && reset_n) begin
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if (enable && reset_n) begin
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if (rw_mem == 1'b0) begin
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if (mem_rw == 1'b0) begin
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reading = 1'b1;
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reading = 1'b1;
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end
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end
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else begin
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else begin
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writing = 1'b1;
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writing = 1'b1;
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