| Line 80... |
Line 80... |
assign data = (mem_rw || !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data.
|
assign data = (mem_rw || !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data.
|
|
|
always @(posedge clk or negedge reset_n) begin // I/O handling
|
always @(posedge clk or negedge reset_n) begin // I/O handling
|
if (reset_n == 1'b0) begin
|
if (reset_n == 1'b0) begin
|
port_a <= 8'h00;
|
port_a <= 8'h00;
|
port_b <= 8'h00;
|
port_b <= 8'b00001000; // D3=1, color!
|
ddra <= 8'h00;
|
ddra <= 8'h00;
|
end
|
end
|
else begin
|
else begin
|
port_b[0] <= ~io_lines[0]; // these two are not actually switches
|
if (io_lines[0]) begin // these are switches
|
port_b[1] <= ~io_lines[1];
|
port_b[0] <= !port_b[0];
|
|
end
|
if (io_lines[3]) begin // these are.
|
if (io_lines[1]) begin
|
|
port_b[1] <= !port_b[1];
|
|
end
|
|
if (io_lines[3]) begin
|
port_b[3] <= !port_b[3];
|
port_b[3] <= !port_b[3];
|
end
|
end
|
if (io_lines[6]) begin
|
if (io_lines[6]) begin
|
port_b[6] <= !port_b[6];
|
port_b[6] <= !port_b[6];
|
end
|
end
|
| Line 127... |
Line 130... |
10'h280: data_drv <= port_a;
|
10'h280: data_drv <= port_a;
|
10'h281: data_drv <= ddra;
|
10'h281: data_drv <= ddra;
|
10'h282: data_drv <= port_b;
|
10'h282: data_drv <= port_b;
|
10'h283: data_drv <= 8'h00; // portb ddr is always input
|
10'h283: data_drv <= 8'h00; // portb ddr is always input
|
10'h284: data_drv <= timer;
|
10'h284: data_drv <= timer;
|
default: data_drv <= ram[address[6:0]];
|
default: data_drv <= ram[address];
|
endcase
|
endcase
|
end
|
end
|
else if (writing) begin // writing!
|
else if (writing) begin // writing!
|
case (address)
|
case (address)
|
|
10'h281: begin
|
|
ddra <= data;
|
|
end
|
10'h294: begin
|
10'h294: begin
|
c1_timer <= 1'b1;
|
c1_timer <= 1'b1;
|
c8_timer <= 1'b0;
|
c8_timer <= 1'b0;
|
c64_timer <= 1'b0;
|
c64_timer <= 1'b0;
|
c1024_timer <= 1'b0;
|
c1024_timer <= 1'b0;
|
| Line 148... |
Line 154... |
c8_timer <= 1'b1;
|
c8_timer <= 1'b1;
|
c64_timer <= 1'b0;
|
c64_timer <= 1'b0;
|
c1024_timer <= 1'b0;
|
c1024_timer <= 1'b0;
|
timer <= data;
|
timer <= data;
|
flipped <= 1'b0;
|
flipped <= 1'b0;
|
counter <= 11'd8;
|
counter <= 11'd7;
|
end
|
end
|
10'h296: begin
|
10'h296: begin
|
c1_timer <= 1'b0;
|
c1_timer <= 1'b0;
|
c8_timer <= 1'b0;
|
c8_timer <= 1'b0;
|
c64_timer <= 1'b1;
|
c64_timer <= 1'b1;
|
c1024_timer <= 1'b0;
|
c1024_timer <= 1'b0;
|
timer <= data;
|
timer <= data;
|
flipped <= 1'b0;
|
flipped <= 1'b0;
|
counter <= 11'd64;
|
counter <= 11'd63;
|
end
|
end
|
10'h297: begin
|
10'h297: begin
|
c1_timer <= 1'b0;
|
c1_timer <= 1'b0;
|
c8_timer <= 1'b0;
|
c8_timer <= 1'b0;
|
c64_timer <= 1'b0;
|
c64_timer <= 1'b0;
|
c1024_timer <= 1'b1;
|
c1024_timer <= 1'b1;
|
timer <= data;
|
timer <= data;
|
flipped <= 1'b0;
|
flipped <= 1'b0;
|
counter <= 11'd1024;
|
counter <= 11'd1023;
|
end
|
end
|
default: begin
|
default: begin
|
ram[address[6:0]] <= data;
|
ram[address] <= data;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
if (!writing_at_timer) begin
|
if (!writing_at_timer) begin
|
if (counter == 11'd0) begin
|
if (flipped || timer == 8'd0) begin // finished counting
|
|
counter <= 11'd0;
|
timer <= timer - 8'd1;
|
timer <= timer - 8'd1;
|
|
|
if (timer == 8'd0) begin
|
|
flipped <= 1'b1;
|
flipped <= 1'b1;
|
end
|
end
|
|
else begin
|
|
if (counter == 11'd0) begin
|
|
timer <= timer - 8'd1;
|
|
|
if (c1_timer || flipped) begin
|
if (c1_timer) begin
|
counter <= 11'd1;
|
counter <= 11'd0;
|
end
|
end
|
if (c8_timer) begin
|
if (c8_timer) begin
|
counter <= 11'd8;
|
counter <= 11'd7;
|
end
|
end
|
if (c64_timer) begin
|
if (c64_timer) begin
|
counter <= 11'd64;
|
counter <= 11'd63;
|
end
|
end
|
if (c1024_timer) begin
|
if (c1024_timer) begin
|
counter <= 11'd1024;
|
counter <= 11'd1023;
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
counter <= counter - 11'd1;
|
counter <= counter - 11'd1;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
end
|
|
|
always @(*) begin // logic for easier controlling
|
always @(*) begin // logic for easier controlling
|
reading = 1'b0;
|
reading = 1'b0;
|
writing = 1'b0;
|
writing = 1'b0;
|
writing_at_timer = 1'b0;
|
writing_at_timer = 1'b0;
|
