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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [test_top.v] - Diff between revs 225 and 226
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module test_top(reset, clk_50, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS);
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module test_top(reset_n, clk_50, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS);
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input reset;
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input reset_n;
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input clk_50;
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input clk_50;
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input [8:0] SW;
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input [8:0] SW;
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output [3:0] VGA_R;
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output [3:0] VGA_R;
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output [3:0] VGA_G;
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output [3:0] VGA_G;
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output [3:0] VGA_B;
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output [3:0] VGA_B;
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output [9:0] LEDR;
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output [9:0] LEDR;
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output VGA_VS;
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output VGA_VS;
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output VGA_HS;
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output VGA_HS;
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//wire [479:0] line;
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wire [479:0] line;
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//wire [4:0] vert_counter;
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wire [4:0] vert_counter;
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vga_controller vga_controller (
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vga_controller vga_controller (
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.reset(reset),
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.reset_n(reset_n),
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.clk_50(clk_50),
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.clk_50(clk_50),
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.line(line),
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.line(line),
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.vert_counter(vert_counter),
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.SW(SW),
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.SW(SW),
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.VGA_R(VGA_R),
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.VGA_R(VGA_R),
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.VGA_G(VGA_G),
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.VGA_G(VGA_G),
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.VGA_B(VGA_B),
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.VGA_B(VGA_B),
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.LEDR(LEDR),
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.LEDR(LEDR),
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.VGA_VS(VGA_VS),
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.VGA_VS(VGA_VS),
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.VGA_HS(VGA_HS)
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.VGA_HS(VGA_HS),
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.vert_counter(vert_counter)
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);
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);
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controller_test controller_test (
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controller_test controller_test (
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.reset(reset),
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.reset_n(reset_n),
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.clk_50(clk_50),
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.clk_50(clk_50),
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.line(line),
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.line(line),
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.vert_counter(vert_counter)
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.vert_counter(vert_counter)
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);
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);
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