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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [vga_controller.v] - Diff between revs 221 and 222
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Rev 222 |
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Line 42... |
//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module vga_controller (
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module vga_controller ( reset, clk_50, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS);
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input reset,
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input reset,
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input clk_50,
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input clk_50,
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input [8:0] SW,
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input [8:0] SW,
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output reg [3:0] VGA_R,
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output reg [3:0] VGA_R,
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output reg [3:0] VGA_G,
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output reg [3:0] VGA_G,
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output reg [3:0] VGA_B,
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output reg [3:0] VGA_B,
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output [9:0] LEDR,
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output [9:0] LEDR,
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output reg VGA_VS,
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output reg VGA_VS,
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output reg VGA_HS
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output reg VGA_HS
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);
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reg clk_25;
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reg clk_25;
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reg [9:0] hc;
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reg [9:0] hc;
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reg [9:0] vc;
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reg [9:0] vc;
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reg vsenable;
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reg vsenable;
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