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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [vga_controller.v] - Diff between revs 223 and 224
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module vga_controller ( reset, clk_50, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS);
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module vga_controller ( reset, clk_50, line, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS);
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input reset;
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input reset;
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input clk_50;
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input clk_50;
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input [8:0] SW;
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input [8:0] SW;
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input [479:0] line;
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output reg [3:0] VGA_R;
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output reg [3:0] VGA_R;
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output reg [3:0] VGA_G;
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output reg [3:0] VGA_G;
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output reg [3:0] VGA_B;
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output reg [3:0] VGA_B;
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output [9:0] LEDR;
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output [9:0] LEDR;
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output reg VGA_VS;
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output reg VGA_VS;
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