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Line 62... |
reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus
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reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus
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assign data = (mem_rw || !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data.
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assign data = (mem_rw || !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data.
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reg VSYNC; // vertical sync set-clear
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reg VSYNC; // vertical sync set-clear
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reg VBLANK; // 1 1 1 vertical blank set-clear
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reg [2:0] VBLANK; // vertical blank set-clear
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reg WSYNC; // s t r o b e wait for leading edge of horizontal blank
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reg WSYNC; // s t r o b e wait for leading edge of horizontal blank
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reg RSYNC; // s t r o b e reset horizontal sync counter
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reg RSYNC; // s t r o b e reset horizontal sync counter
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reg NUSIZ0; // 1 1 1 1 1 1 number-size player-missile 0
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reg [5:0] NUSIZ0; // number-size player-missile 0
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reg NUSIZ1; // 1 1 1 1 1 1 number-size player-missile 1
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reg [5:0] NUSIZ1; // number-size player-missile 1
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reg COLUP0; // 1 1 1 1 1 1 1 color-lum player 0
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reg [6:0] COLUP0; // color-lum player 0
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reg COLUP1; // 1 1 1 1 1 1 1 color-lum player 1
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reg [6:0] COLUP1; // color-lum player 1
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reg COLUPF; // 1 1 1 1 1 1 1 color-lum playfield
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reg [6:0] COLUPF; // color-lum playfield
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reg COLUBK; // 1 1 1 1 1 1 1 color-lum background
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reg [6:0] COLUBK; // color-lum background
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reg CTRLPF; // 1 1 1 1 1 control playfield ball size & collisions
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reg [4:0] CTRLPF; // control playfield ball size & collisions
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reg REFP0; // 1 reflect player 0
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reg REFP0; // reflect player 0
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reg REFP1; // 1 reflect player 1
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reg REFP1; // reflect player 1
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reg PF0; // 1 1 1 1 playfield register byte 0
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reg [3:0] PF0; // playfield register byte 0
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reg PF1; // 1 1 1 1 1 1 1 1 playfield register byte 1
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reg [7:0] PF1; // playfield register byte 1
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reg PF2; // 1 1 1 1 1 1 1 1 playfield register byte 2
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reg [7:0] PF2; // playfield register byte 2
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reg RESP0; // s t r o b e reset player 0
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reg RESP0; // s t r o b e reset player 0
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reg RESP1; // s t r o b e reset player 1
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reg RESP1; // s t r o b e reset player 1
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reg RESM0; // s t r o b e reset missile 0
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reg RESM0; // s t r o b e reset missile 0
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reg RESM1; // s t r o b e reset missile 1
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reg RESM1; // s t r o b e reset missile 1
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reg RESBL; // s t r o b e reset ball
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reg RESBL; // s t r o b e reset ball
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reg AUDC0; // 1 1 1 1 audio control 0
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reg [3:0] AUDC0; // audio control 0
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reg AUDC1; // 1 1 1 1 1 audio control 1
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reg [4:0] AUDC1; // audio control 1
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reg AUDF0; // 1 1 1 1 1 audio frequency 0
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reg [4:0] AUDF0; // audio frequency 0
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reg AUDF1; // 1 1 1 1 audio frequency 1
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reg [3:0] AUDF1; // audio frequency 1
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reg AUDV0; // 1 1 1 1 audio volume 0
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reg [3:0] AUDV0; // audio volume 0
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reg AUDV1; // 1 1 1 1 audio volume 1
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reg [3:0] AUDV1; // audio volume 1
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reg GRP0; // 1 1 1 1 1 1 1 1 graphics player 0
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reg [7:0] GRP0; // graphics player 0
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reg GRP1; // 1 1 1 1 1 1 1 1 graphics player 1
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reg [7:0] GRP1; // graphics player 1
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reg ENAM0; // 1 graphics (enable) missile 0
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reg ENAM0; // graphics (enable) missile 0
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reg ENAM1; // 1 graphics (enable) missile 1
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reg ENAM1; // graphics (enable) missile 1
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reg ENABL; // 1 graphics (enable) ball
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reg ENABL; // graphics (enable) ball
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reg HMP0; // 1 1 1 1 horizontal motion player 0
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reg [3:0] HMP0; // horizontal motion player 0
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reg HMP1; // 1 1 1 1 horizontal motion player 1
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reg [3:0] HMP1; // horizontal motion player 1
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reg HMM0; // 1 1 1 1 horizontal motion missile 0
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reg [3:0] HMM0; // horizontal motion missile 0
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reg HMM1; // 1 1 1 1 horizontal motion missile 1
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reg [3:0] HMM1; // horizontal motion missile 1
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reg HMBL; // 1 1 1 1 horizontal motion ball
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reg [3:0] HMBL; // horizontal motion ball
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reg VDELP0; // 1 vertical delay player 0
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reg VDELP0; // vertical delay player 0
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reg VDEL01; // 1 vertical delay player 1
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reg VDEL01; // vertical delay player 1
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reg VDELBL; // 1 vertical delay ball
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reg VDELBL; // vertical delay ball
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reg RESMP0; // 1 reset missile 0 to player 0
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reg RESMP0; // reset missile 0 to player 0
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reg RESMP1; // 1 reset missile 1 to player 1
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reg RESMP1; // reset missile 1 to player 1
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reg HMOVE; // s t r o b e apply horizontal motion
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reg HMOVE; // s t r o b e apply horizontal motion
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reg HMCLR; // s t r o b e clear horizontal motion registers
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reg HMCLR; // s t r o b e clear horizontal motion registers
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reg CXCLR ; // s t r o b e clear collision latches
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reg CXCLR ; // s t r o b e clear collision latches
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always @(posedge clk or negedge reset_n) begin // R/W register/memory handling
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reg [1:0] CXM0P; // read collision MO P1 M0 P0
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reg [1:0] CXM1P; // read collision M1 P0 M1 P1
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reg [1:0] CXP0FB; // read collision P0 PF P0 BL
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reg [1:0] CXP1FB; // read collision P1 PF P1 BL
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reg [1:0] CXM0FB; // read collision M0 PF M0 BL
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reg [1:0] CXM1FB; // read collision M1 PF M1 BL
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reg CXBLPF; // read collision BL PF unused
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reg [1:0] CXPPMM; // read collision P0 P1 M0 M1
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reg INPT0; // read pot port
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reg INPT1; // read pot port
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reg INPT2; // read pot port
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reg INPT3; // read pot port
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reg INPT4; // read input
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reg INPT5; // read input
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always @(posedge clk or negedge reset_n) begin
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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data_drv <= 8'h00;
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data_drv <= 8'h00;
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end
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end
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else begin
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else begin
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if (reading) begin // reading!
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if (mem_rw == 1'b0) begin // reading!
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case (address)
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case (address)
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10'h280: data_drv <= port_a;
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6'h00: data_drv <= {CXM0P, 6'b000000};
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10'h281: data_drv <= ddra;
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6'h01: data_drv <= {CXM1P, 6'b000000};
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10'h282: data_drv <= port_b;
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6'h02: data_drv <= {CXP0FB, 6'b000000};
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10'h283: data_drv <= 8'h00; // portb ddr is always input
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6'h03: data_drv <= {CXP1FB, 6'b000000};
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10'h284: data_drv <= timer;
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6'h04: data_drv <= {CXM0FB, 6'b000000};
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default: data_drv <= ram[address];
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6'h05: data_drv <= {CXM1FB, 6'b000000};
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6'h06: data_drv <= {CXBLPF, 7'b000000};
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6'h07: data_drv <= {CXPPMM, 6'b000000};
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6'h08: data_drv <= {INPT0, 7'b000000};
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6'h09: data_drv <= {INPT1, 7'b000000};
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6'h0A: data_drv <= {INPT2, 7'b000000};
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6'h0B: data_drv <= {INPT3, 7'b000000};
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6'h0C: data_drv <= {INPT4, 7'b000000};
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6'h0D: data_drv <= {INPT5, 7'b000000};
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default: ;
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endcase
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endcase
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end
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end
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else if (writing) begin // writing!
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else begin // writing!
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case (address)
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case (address)
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10'h281: begin
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6'h00: begin
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ddra <= data;
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VSYNC <= data;
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end
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10'h294: begin
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c1_timer <= 1'b1;
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c8_timer <= 1'b0;
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c64_timer <= 1'b0;
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c1024_timer <= 1'b0;
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timer <= data;
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flipped <= 1'b0;
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counter <= 11'd1;
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end
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10'h295: begin
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c1_timer <= 1'b0;
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c8_timer <= 1'b1;
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c64_timer <= 1'b0;
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c1024_timer <= 1'b0;
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timer <= data;
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flipped <= 1'b0;
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counter <= 11'd7;
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end
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10'h296: begin
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c1_timer <= 1'b0;
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c8_timer <= 1'b0;
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c64_timer <= 1'b1;
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c1024_timer <= 1'b0;
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timer <= data;
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flipped <= 1'b0;
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counter <= 11'd63;
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end
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10'h297: begin
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c1_timer <= 1'b0;
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c8_timer <= 1'b0;
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c64_timer <= 1'b0;
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c1024_timer <= 1'b1;
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timer <= data;
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flipped <= 1'b0;
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counter <= 11'd1023;
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end
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default: begin
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ram[address] <= data;
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end
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end
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endcase
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6'h01: begin
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end
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VBLANK <= data;
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if (!writing_at_timer) begin
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if (flipped || timer == 8'd0) begin // finished counting
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counter <= 11'd0;
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timer <= timer - 8'd1;
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flipped <= 1'b1;
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end
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end
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else begin
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6'h02: begin
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if (counter == 11'd0) begin
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WSYNC <= data;
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timer <= timer - 8'd1;
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if (c1_timer) begin
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counter <= 11'd0;
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end
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end
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if (c8_timer) begin
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6'h03: begin
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counter <= 11'd7;
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RSYNC <= data;
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end
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end
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if (c64_timer) begin
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6'h04: begin
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counter <= 11'd63;
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NUSIZ0 <= data;
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end
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end
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if (c1024_timer) begin
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6'h05: begin
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counter <= 11'd1023;
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NUSIZ1 <= data;
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end
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end
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6'h06: begin
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COLUP0 <= data;
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end
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end
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else begin
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6'h07: begin
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counter <= counter - 11'd1;
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COLUP1 <= data;
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end
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end
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6'h08: begin
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COLUPF <= data;
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end
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end
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6'h09: begin
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COLUBK <= data;
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end
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end
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6'h0a: begin
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CTRLPF <= data;
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end
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end
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6'h0b: begin
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NUSIZ1 <= data;
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end
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end
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6'h0c: begin
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always @(*) begin // logic for easier controlling
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NUSIZ1 <= data;
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reading = 1'b0;
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writing = 1'b0;
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writing_at_timer = 1'b0;
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if (enable && reset_n) begin
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if (mem_rw == 1'b0) begin
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reading = 1'b1;
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end
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end
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else begin
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default: begin
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writing = 1'b1;
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if ( (address == 10'h294) || (address == 10'h295) || (address == 10'h296) || (address == 10'h297) ) begin
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writing_at_timer = 1'b1;
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end
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end
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endcase
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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