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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module video(clk, reset_n, io_lines, enable, mem_rw, address, data);
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module video(clk, reset_n, io_lines, enable, mem_rw, address, data, pixel);
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] ADDR_SIZE = 4'd10; // this is the *local* addr_size
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parameter [3:0] ADDR_SIZE = 4'd10; // this is the *local* addr_size
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
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localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
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localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
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input [15:0] io_lines; // inputs from the keyboard controller
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input [15:0] io_lines; // inputs from the keyboard controller
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input enable; // since the address bus is shared an enable signal is used
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input enable; // since the address bus is shared an enable signal is used
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input mem_rw; // read == 0, write == 1
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input mem_rw; // read == 0, write == 1
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input [ADDR_SIZE_:0] address; // system address bus
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input [ADDR_SIZE_:0] address; // system address bus
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inout [DATA_SIZE_:0] data; // controler <=> riot data bus
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inout [DATA_SIZE_:0] data; // controler <=> riot data bus
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output [11:0] pixel;
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reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus
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reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus
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assign data = (mem_rw || !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data.
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assign data = (mem_rw || !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data.
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reg VSYNC; // vertical sync set-clear
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reg VSYNC; // vertical sync set-clear
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reg [2:0] VBLANK; // vertical blank set-clear
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reg [2:0] VBLANK; // vertical blank set-clear
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reg WSYNC; // s t r o b e wait for leading edge of horizontal blank
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reg WSYNC; // SEMI-strobe wait for leading edge of horizontal blank
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reg RSYNC; // s t r o b e reset horizontal sync counter
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reg RSYNC; // s t r o b e reset horizontal sync counter
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reg [5:0] NUSIZ0; // number-size player-missile 0
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reg [5:0] NUSIZ0; // number-size player-missile 0
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reg [5:0] NUSIZ1; // number-size player-missile 1
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reg [5:0] NUSIZ1; // number-size player-missile 1
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reg [6:0] COLUP0; // color-lum player 0
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reg [6:0] COLUP0; // color-lum player 0
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reg [6:0] COLUP1; // color-lum player 1
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reg [6:0] COLUP1; // color-lum player 1
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reg INPT2; // read pot port
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reg INPT2; // read pot port
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reg INPT3; // read pot port
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reg INPT3; // read pot port
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reg INPT4; // read input
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reg INPT4; // read input
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reg INPT5; // read input
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reg INPT5; // read input
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reg [5:0] hor_counter; // this counter is the "current pixel". when it reaches 39 the wsync register must be driven to zero
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always @(posedge clk or negedge reset_n) begin
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if (reset_n == 1'b0) begin
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hor_counter <= 6'd0;
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end
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else begin
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if (hor_counter == 6'd39) begin
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hor_counter <= 6'd0;
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WSYNC <= 1'b0;
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end
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else begin
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hor_counter <= hor_counter + 6'd1;
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end
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end
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end
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always @(posedge clk or negedge reset_n) begin
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always @(posedge clk or negedge reset_n) begin
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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data_drv <= 8'h00;
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data_drv <= 8'h00;
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WSYNC <= 1'b0;
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end
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end
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else begin
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else begin
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if (mem_rw == 1'b0) begin // reading!
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if (mem_rw == 1'b0) begin // reading!
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case (address)
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case (address)
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6'h00: data_drv <= {CXM0P, 6'b000000};
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6'h00: data_drv <= {CXM0P, 6'b000000};
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