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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Video module ////
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//// Video module ////
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//// ////
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//// ////
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//// TODO: ////
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//// TODO: ////
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//// - Everything? ////
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//// - Collision detection ////
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//// - Pixel output ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// ////
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//// ////
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module video(clk, reset_n, io_lines, enable, mem_rw, address, data, pixel);
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module video(clk, reset_n, io_lines, enable, mem_rw, address, data, pixel, write_addr, write_data, write_enable_n);
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] ADDR_SIZE = 4'd10; // this is the *local* addr_size
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parameter [3:0] ADDR_SIZE = 4'd10; // this is the *local* addr_size
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
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localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
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localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
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input reset_n;
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input reset_n;
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input [15:0] io_lines; // inputs from the keyboard controller
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input [15:0] io_lines; // inputs from the keyboard controller
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input enable; // since the address bus is shared an enable signal is used
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input enable; // since the address bus is shared an enable signal is used
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input mem_rw; // read == 0, write == 1
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input mem_rw; // read == 0, write == 1
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input [ADDR_SIZE_:0] address; // system address bus
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input [ADDR_SIZE_:0] address; // system address bus
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inout [DATA_SIZE_:0] data; // controler <=> riot data bus
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inout [DATA_SIZE_:0] data; // controler <=> video data bus
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output [11:0] pixel;
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output reg [2:0] pixel;
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output reg [10:0] write_addr; // for the video memory
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output reg [2:0] write_data;
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output reg write_enable_n;
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reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus
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reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus
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assign data = (mem_rw || !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data.
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assign data = (mem_rw || !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data.
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reg REFP0; // reflect player 0
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reg REFP0; // reflect player 0
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reg REFP1; // reflect player 1
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reg REFP1; // reflect player 1
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reg [3:0] PF0; // playfield register byte 0
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reg [3:0] PF0; // playfield register byte 0
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reg [7:0] PF1; // playfield register byte 1
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reg [7:0] PF1; // playfield register byte 1
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reg [7:0] PF2; // playfield register byte 2
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reg [7:0] PF2; // playfield register byte 2
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reg RESP0; // s t r o b e reset player 0
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//reg RESP0; // s t r o b e reset player 0
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reg RESP1; // s t r o b e reset player 1
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reg RESP1; // s t r o b e reset player 1
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reg RESM0; // s t r o b e reset missile 0
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reg RESM0; // s t r o b e reset missile 0
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reg RESM1; // s t r o b e reset missile 1
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reg RESM1; // s t r o b e reset missile 1
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reg RESBL; // s t r o b e reset ball
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reg RESBL; // s t r o b e reset ball
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reg [3:0] AUDC0; // audio control 0
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reg [3:0] AUDC0; // audio control 0
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reg INPT2; // read pot port
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reg INPT2; // read pot port
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reg INPT3; // read pot port
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reg INPT3; // read pot port
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reg INPT4; // read input
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reg INPT4; // read input
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reg INPT5; // read input
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reg INPT5; // read input
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reg [5:0] hor_counter; // this counter is the "current pixel". when it reaches 39 the wsync register must be driven to zero
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reg [8:0] vert_counter;
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reg [7:0] hor_counter;
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always @(posedge clk or negedge reset_n) begin
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always @(posedge clk or negedge reset_n) begin
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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hor_counter <= 6'd0;
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hor_counter <= 8'd0;
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vert_counter <= 9'd0;
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end
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end
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else begin
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else begin
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if (hor_counter == 6'd39) begin
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if (hor_counter == 8'd227) begin
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hor_counter <= 6'd0;
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hor_counter <= 8'd0;
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WSYNC <= 1'b0;
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WSYNC <= 1'b0; // TODO: check this on stella pdf
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if (vert_counter == 9'd261) begin
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vert_counter <= 9'd0;
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end
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else begin
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vert_counter <= vert_counter + 9'd1;
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end
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end
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end
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else begin
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else begin
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hor_counter <= hor_counter + 6'd1;
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hor_counter <= hor_counter + 6'd1;
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end
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end
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end
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end
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always @(posedge clk or negedge reset_n) begin
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always @(posedge clk or negedge reset_n) begin
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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data_drv <= 8'h00;
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data_drv <= 8'h00;
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WSYNC <= 1'b0;
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WSYNC <= 1'b0;
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end
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end
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else begin
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else if (enable == 1'b1) begin
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if (mem_rw == 1'b0) begin // reading!
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if (mem_rw == 1'b0) begin // reading!
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case (address)
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case (address)
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6'h00: data_drv <= {CXM0P, 6'b000000};
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6'h00: data_drv <= {CXM0P, 6'b000000};
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6'h01: data_drv <= {CXM1P, 6'b000000};
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6'h01: data_drv <= {CXM1P, 6'b000000};
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6'h02: data_drv <= {CXP0FB, 6'b000000};
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6'h02: data_drv <= {CXP0FB, 6'b000000};
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end
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end
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6'h0f: begin
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6'h0f: begin
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PF2 <= data;
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PF2 <= data;
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end
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end
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6'h10: begin
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6'h10: begin
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RESP0 <= 1'b1; // STROBE
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//RESP0 <= 1'b1; // STROBE
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end
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end
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6'h11: begin
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6'h11: begin
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RESP1 <= 1'b1; // STROBE
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RESP1 <= 1'b1; // STROBE
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end
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end
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6'h12: begin
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6'h12: begin
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endcase
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endcase
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end
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end
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end
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end
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end
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end
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reg draw_p0;
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reg draw_p1;
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reg draw_m0;
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reg draw_m1;
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reg draw_bl;
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always @ (*) begin // always combinational block that handles strobe register
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draw_p0 = 1'b0;
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draw_p1 = 1'b0;
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draw_m0 = 1'b0;
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draw_m1 = 1'b0;
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draw_bl = 1'b0;
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if (enable == 1'b1 && mem_rw == 1'b1) begin // writing!
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case (address)
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6'h10: begin
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draw_p0 = 1'b1;
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end
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6'h11: begin
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draw_p1 = 1'b1;
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end
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6'h12: begin
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draw_m0 = 1'b1;
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end
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6'h13: begin
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draw_m1 = 1'b1;
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end
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6'h14: begin
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draw_bl = 1'b1;
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end
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endcase
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end
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end
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always @(*) begin // comb logic
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if (hor_counter < 68 || vert_counter < 40 || vert_counter > 232) begin
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pixel = 3'd0;
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write_enable_n = 1'b1;
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write_addr = 0;
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write_data = vert_counter[2:0];
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end
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else begin
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write_enable_n = 1'b0;
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write_addr = (hor_counter - 68) + (vert_counter - 40)*160;
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write_data = 3'd4;
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if (CTRLPF[2] == 1'b1) begin // playfield gets priority over players so they can move behind the playfield
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// Priority Objects
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// 1 PF, BL
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// 2 P0, M0
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// 3 P1, M1
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// 4 BK
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end
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else begin // regular priority
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// Priority Objects
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// 1 P0, M0
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// 2 P1, M1
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// 3 BL, PF
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// 4 BK
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if (CTRLPF[0] == 1'b1) begin// reflected PF
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if (ENABL == 1'b1) begin // the ball is enabled
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end
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else begin
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if (vert_counter < 4) begin
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pixel = (PF0[vert_counter] == 1'b1) ? COLUPF : COLUBK;
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end
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else if (vert_counter < 12) begin
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pixel = (PF1[vert_counter - 4] == 1'b1) ? COLUPF : COLUBK;
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end
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else if (vert_counter < 20) begin
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pixel = (PF2[vert_counter - 12] == 1'b1) ? COLUPF : COLUBK;
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end
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else if (vert_counter < 28) begin
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pixel = (PF2[vert_counter - 20] == 1'b1) ? COLUPF : COLUBK;
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end
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else if (vert_counter < 36) begin
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pixel = (PF1[vert_counter - 28] == 1'b1) ? COLUPF : COLUBK;
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end
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else begin
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pixel = (PF0[vert_counter - 36] == 1'b1) ? COLUPF : COLUBK;
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end
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end
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end
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else begin
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if (vert_counter < 4) begin
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pixel = (PF0[vert_counter] == 1'b1) ? COLUPF : COLUBK;
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end
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else if (vert_counter < 12) begin
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pixel = (PF1[vert_counter - 4] == 1'b1) ? COLUPF : COLUBK;
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end
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else if (vert_counter < 20) begin
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pixel = (PF2[vert_counter - 12] == 1'b1) ? COLUPF : COLUBK;
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end
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else if (vert_counter < 24) begin
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pixel = (PF0[vert_counter - 20] == 1'b1) ? COLUPF : COLUBK;
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end
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else if (vert_counter < 32) begin
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pixel = (PF1[vert_counter - 24] == 1'b1) ? COLUPF : COLUBK;
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end
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else begin
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pixel = (PF2[vert_counter - 32] == 1'b1) ? COLUPF : COLUBK;
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end
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end
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end
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// 1: ordem de avaliacao
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// 2: pinta da cor do objeto
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// 3: senao pinta de bk
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pixel = 3'd4;
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end
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end
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endmodule
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endmodule
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