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# Cadence Encounter(R) RTL Compiler
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# Cadence Encounter(R) RTL Compiler
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set SVNPATH /home/nscad/samuel/Desktop/svn_atari/trunk/
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set SVNPATH /home/nscad/samuel/Desktop/svn_atari/trunk/
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set FILE_LIST {t6507lp.v t6507lp_alu.v t6507lp_fsm.v}
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set FILE_LIST {t6507lp.v t6507lp_alu.v t6507lp_fsm.v}
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set_attr lp_insert_clock_gating true /
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set_attribute lp_insert_operand_isolation true /
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set_attribute hdl_search_path $SVNPATH/rtl/verilog/
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set_attribute hdl_search_path $SVNPATH/rtl/verilog/
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set_attr lib_search_path $SVNPATH/syn/cadence/libs/
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set_attr lib_search_path $SVNPATH/syn/cadence/libs/
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read_hdl $FILE_LIST -v2001
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read_hdl $FILE_LIST -v2001
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set_attr library { D_CELLS_3_3V.lib D_CELLSL_3_3V.lib }
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set_attr library { D_CELLS_3_3V.lib D_CELLSL_3_3V.lib }
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set_attribute avoid false [find / -libcell LGC*]
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set_attribute avoid false [find / -libcell LSG*]
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set_attribute avoid false [find / -libcell LSOGC*]
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set_attribute lef_library {xc06_m3_FE.lef D_CELLS.lef D_CELLSL.lef}
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set_attr cap_table_file xc06m3_typ.CapTbl
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set_attr interconnect_mode ple /
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elaborate
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elaborate
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check_design -unresolved
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define_clock -period 1000000 -name 1MHz [find [ find / -design t6507lp] -port clk]
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define_clock -period 1000000 -name 1MHz [find [ find / -design t6507lp] -port clk]
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set_attribute lp_insert_operand_isolation true
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set_attribute slew {0 0 1 1} [find / -clock 1MHz]
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set_attr lp_insert_clock_gating true
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#clock gating enable, check e-mail
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read_vcd simvision.vcd
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#synthesize -effort high
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synthesize -to_generic -effort high
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synthesize -to_mapped -effort high -incremental
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write_hdl t6507lp > ../results/t6507lp.vg
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#check_design
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synthesize -to_generic -effort high
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synthesize -to_mapped -effort high -no_incremental
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clock_gating share
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synthesize -incremental -effort high
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#reports
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write_encounter design -basename /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/t6507lp t6507lp
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#report area
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#write_hdl t6507lp > ../results/t6507lp.vg
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