| Line 7... |
Line 7... |
set_attr lp_insert_clock_gating true /
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set_attr lp_insert_clock_gating true /
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set_attribute lp_insert_operand_isolation true /
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set_attribute lp_insert_operand_isolation true /
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|
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set_attribute hdl_search_path $SVNPATH/rtl/verilog/
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set_attribute hdl_search_path $SVNPATH/rtl/verilog/
|
set_attr lib_search_path $SVNPATH/syn/cadence/libs/
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set_attr lib_search_path $SVNPATH/syn/cadence/libs/
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read_hdl $FILE_LIST -v2001
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read_hdl $FILE_LIST -v2001
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set_attr library { D_CELLS_3_3V.lib D_CELLSL_3_3V.lib}
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set_attr library { D_CELLS_3_3V.lib D_CELLSL_3_3V.lib}
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|
|
set_attribute avoid false [find / -libcell LGC*]
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#set_attribute avoid false [find / -libcell LGC*]
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set_attribute avoid false [find / -libcell LSG*]
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#set_attribute avoid false [find / -libcell LSG*]
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set_attribute avoid false [find / -libcell LSOGC*]
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#set_attribute avoid false [find / -libcell LSOGC*]
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|
|
set_attribute lef_library {xc06_m3_FE.lef D_CELLS.lef D_CELLSL.lef}
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set_attribute lef_library {xc06_m3_FE.lef D_CELLS.lef D_CELLSL.lef}
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set_attr cap_table_file xc06m3_typ.CapTbl
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set_attr cap_table_file xc06m3_typ.CapTbl
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set_attr interconnect_mode ple /
|
set_attr interconnect_mode ple /
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|
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| Line 32... |
Line 33... |
synthesize -to_mapped -effort high -no_incremental
|
synthesize -to_mapped -effort high -no_incremental
|
clock_gating share
|
clock_gating share
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synthesize -incremental -effort high
|
synthesize -incremental -effort high
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|
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write_encounter design -basename /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/t6507lp t6507lp
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write_encounter design -basename /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/t6507lp t6507lp
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#write_hdl t6507lp > ../results/t6507lp.vg
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