URL https://opencores.org/ocsvn/t80/t80/trunk

Subversion Repositories t80

[/] [t80/] [trunk/] [rtl/] [vhdl/] [DebugSystem.vhd] - Diff between revs 12 and 20

Rev 12	Rev 20
Line 26...	Line 26...
`DTR0 : out std_logic;`	`DTR0 : out std_logic;`
`TXD1 : out std_logic;`	`TXD1 : out std_logic;`
`RTS1 : out std_logic;`	`RTS1 : out std_logic;`
`DTR1 : out std_logic`	`DTR1 : out std_logic`
`);`	`);`
`end entity DebugSystem;`	`end DebugSystem;`

`architecture struct of DebugSystem is`	`architecture struct of DebugSystem is`

`signal M1_n : std_logic;`	`signal M1_n : std_logic;`
`signal MREQ_n : std_logic;`	`signal MREQ_n : std_logic;`
Line 91...	Line 91...
`UART0_D when UART0CS_n = '0' else`	`UART0_D when UART0CS_n = '0' else`
`UART1_D when UART1CS_n = '0' else`	`UART1_D when UART1CS_n = '0' else`
`ROM_D;`	`ROM_D;`

`u0 : entity work.T80s`	`u0 : entity work.T80s`
`generic map(Mode => 1)`	`generic map(Mode => 1, T2Write => 1)`
`port map(`	`port map(`
`RESET_n => RESET_s,`	`RESET_n => RESET_s,`
`CLK_n => Clk,`	`CLK_n => Clk,`
`WAIT_n => WAIT_n,`	`WAIT_n => WAIT_n,`
`INT_n => INT_n,`	`INT_n => INT_n,`