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[/] [t80/] [trunk/] [rtl/] [vhdl/] [SSRAM.vhd] - Diff between revs 16 and 46
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| Rev 16 |
Rev 46 |
| Line 69... |
Line 69... |
architecture behaviour of SSRAM is
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architecture behaviour of SSRAM is
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type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
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type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
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signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1);
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signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1);
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signal A_r : std_logic_vector(AddrWidth - 1 downto 0);
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signal A_r : std_logic_vector(AddrWidth - 1 downto 0);
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signal B : std_logic_vector(AddrWidth - 1 downto 0);
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begin
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begin
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process (Clk)
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process (Clk)
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begin
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begin
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if Clk'event and Clk = '1' then
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if Clk'event and Clk = '1' then
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if (CE_n nor WE_n) = '1' then
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if (CE_n nor WE_n) = '1' then
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RAM(to_integer(unsigned(B))) <= DIn;
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RAM(to_integer(unsigned(A))) <= DIn;
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end if;
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end if;
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A_r <= A;
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A_r <= A;
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B <= A;
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end if;
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end if;
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end process;
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end process;
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DOut <= RAM(to_integer(unsigned(A_r)))
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DOut <= RAM(to_integer(unsigned(A_r)))
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-- pragma translate_off
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-- pragma translate_off
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