URL
https://opencores.org/ocsvn/t80/t80/trunk
[/] [t80/] [trunk/] [rtl/] [vhdl/] [SSRAM.vhd] - Diff between revs 16 and 46
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 16 |
Rev 46 |
| Line 69... |
Line 69... |
architecture behaviour of SSRAM is
|
architecture behaviour of SSRAM is
|
|
|
type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
|
type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
|
signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1);
|
signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1);
|
signal A_r : std_logic_vector(AddrWidth - 1 downto 0);
|
signal A_r : std_logic_vector(AddrWidth - 1 downto 0);
|
signal B : std_logic_vector(AddrWidth - 1 downto 0);
|
|
|
|
begin
|
begin
|
|
|
process (Clk)
|
process (Clk)
|
begin
|
begin
|
if Clk'event and Clk = '1' then
|
if Clk'event and Clk = '1' then
|
if (CE_n nor WE_n) = '1' then
|
if (CE_n nor WE_n) = '1' then
|
RAM(to_integer(unsigned(B))) <= DIn;
|
RAM(to_integer(unsigned(A))) <= DIn;
|
end if;
|
end if;
|
A_r <= A;
|
A_r <= A;
|
B <= A;
|
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
DOut <= RAM(to_integer(unsigned(A_r)))
|
DOut <= RAM(to_integer(unsigned(A_r)))
|
-- pragma translate_off
|
-- pragma translate_off
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.