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[/] [t80/] [trunk/] [rtl/] [vhdl/] [SSRAMX.vhd] - Diff between revs 27 and 34
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Rev 34 |
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--
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--
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-- Xilinx Block RAM, 8 bit wide and variable size (Min. 512 bytes)
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-- Xilinx Block RAM, 8 bit wide and variable size (Min. 512 bytes)
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--
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--
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-- Version : 0240
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-- Version : 0242
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--
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--
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-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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--
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--
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-- File history :
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-- File history :
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--
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--
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-- 0240 : Initial release
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-- 0240 : Initial release
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--
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--
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-- 0240 : Changed RAMB4_S8 to map by name
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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library UNISIM;
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library UNISIM;
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bG1: for I in 0 to RAMs - 1 generate
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bG1: for I in 0 to RAMs - 1 generate
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begin
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begin
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WEA(I) <= '1' when (CE_n nor WE_n) = '1' and biA_r = I else '0';
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WEA(I) <= '1' when (CE_n nor WE_n) = '1' and biA_r = I else '0';
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BSSRAM : RAMB4_S8
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BSSRAM : RAMB4_S8
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port map (DIn, '1', WEA(I), '0', Clk, A_i, bRAMOut(I));
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port map(
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DI => DIn,
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EN => '1',
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WE => WEA(I),
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RST => '0',
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CLK => Clk,
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ADDR => A_i,
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DO => bRAMOut(I));
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end generate;
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end generate;
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process (biA_r, bRAMOut)
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process (biA_r, bRAMOut)
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begin
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begin
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DOut <= bRAMOut(0);
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DOut <= bRAMOut(0);
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