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[/] [t80/] [trunk/] [rtl/] [vhdl/] [SSRAMX.vhd] - Diff between revs 34 and 41
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--
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--
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-- Xilinx Block RAM, 8 bit wide and variable size (Min. 512 bytes)
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-- Xilinx Block RAM, 8 bit wide and variable size (Min. 512 bytes)
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--
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--
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-- Version : 0242
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-- Version : 0247
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--
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--
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-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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--
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--
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-- File history :
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-- File history :
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--
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--
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-- 0240 : Initial release
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-- 0240 : Initial release
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--
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--
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-- 0240 : Changed RAMB4_S8 to map by name
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-- 0242 : Changed RAMB4_S8 to map by name
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--
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-- 0247 : Added RAMB4_S8 component declaration
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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library UNISIM;
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use UNISIM.vcomponents.all;
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entity SSRAM is
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entity SSRAM is
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generic(
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generic(
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AddrWidth : integer := 11;
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AddrWidth : integer := 11;
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DataWidth : integer := 8
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DataWidth : integer := 8
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);
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);
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end SSRAM;
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end SSRAM;
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architecture rtl of SSRAM is
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architecture rtl of SSRAM is
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component RAMB4_S8
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port(
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DO : out std_logic_vector(7 downto 0);
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ADDR : in std_logic_vector(8 downto 0);
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CLK : in std_ulogic;
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DI : in std_logic_vector(7 downto 0);
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EN : in std_ulogic;
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RST : in std_ulogic;
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WE : in std_ulogic);
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end component;
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constant RAMs : integer := (2 ** AddrWidth) / 512;
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constant RAMs : integer := (2 ** AddrWidth) / 512;
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type bRAMOut_a is array(0 to RAMs - 1) of std_logic_vector(7 downto 0);
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type bRAMOut_a is array(0 to RAMs - 1) of std_logic_vector(7 downto 0);
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signal bRAMOut : bRAMOut_a;
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signal bRAMOut : bRAMOut_a;
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