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[/] [t80/] [trunk/] [rtl/] [vhdl/] [SSRAMX.vhd] - Diff between revs 41 and 46
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| Rev 41 |
Rev 46 |
| Line 88... |
Line 88... |
type bRAMOut_a is array(0 to RAMs - 1) of std_logic_vector(7 downto 0);
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type bRAMOut_a is array(0 to RAMs - 1) of std_logic_vector(7 downto 0);
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signal bRAMOut : bRAMOut_a;
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signal bRAMOut : bRAMOut_a;
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signal biA_r : integer;
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signal biA_r : integer;
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signal A_r : unsigned(A'left downto 0);
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signal A_r : unsigned(A'left downto 0);
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signal A_i : std_logic_vector(8 downto 0);
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-- signal A_i : std_logic_vector(8 downto 0);
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signal WEA : std_logic_vector(RAMs - 1 downto 0);
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signal WEA : std_logic_vector(RAMs - 1 downto 0);
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begin
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begin
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process (Clk)
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process (Clk)
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| Line 101... |
Line 101... |
A_r <= unsigned(A);
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A_r <= unsigned(A);
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end if;
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end if;
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end process;
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end process;
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biA_r <= to_integer(A_r(A'left downto 9));
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biA_r <= to_integer(A_r(A'left downto 9));
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A_i <= std_logic_vector(A_r(8 downto 0)) when (CE_n nor WE_n) = '1' else A(8 downto 0);
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-- A_i <= std_logic_vector(A_r(8 downto 0)) when (CE_n nor WE_n) = '1' else A(8 downto 0);
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bG1: for I in 0 to RAMs - 1 generate
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bG1: for I in 0 to RAMs - 1 generate
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begin
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begin
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WEA(I) <= '1' when (CE_n nor WE_n) = '1' and biA_r = I else '0';
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WEA(I) <= '1' when (CE_n nor WE_n) = '1' and biA_r = I else '0';
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BSSRAM : RAMB4_S8
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BSSRAM : RAMB4_S8
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| Line 113... |
Line 113... |
DI => DIn,
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DI => DIn,
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EN => '1',
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EN => '1',
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WE => WEA(I),
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WE => WEA(I),
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RST => '0',
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RST => '0',
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CLK => Clk,
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CLK => Clk,
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ADDR => A_i,
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ADDR => A,
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DO => bRAMOut(I));
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DO => bRAMOut(I));
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end generate;
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end generate;
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process (biA_r, bRAMOut)
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process (biA_r, bRAMOut)
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begin
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begin
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