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--
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--
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-- 16450 compatible UART with synchronous bus interface
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-- 16450 compatible UART with synchronous bus interface
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-- RClk/BaudOut is XIn enable instead of actual clock
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-- RClk/BaudOut is XIn enable instead of actual clock
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--
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--
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-- Version : 0249
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-- Version : 0249b
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--
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--
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-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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-- 0208 : First release
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-- 0208 : First release
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--
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--
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-- 0249 : Fixed interrupt and baud rate bugs found by Andy Dyer
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-- 0249 : Fixed interrupt and baud rate bugs found by Andy Dyer
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-- Added modem status and break detection
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-- Added modem status and break detection
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-- Added support for 1.5 and 2 stop bits
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-- Added support for 1.5 and 2 stop bits
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--
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-- 0249b : Fixed loopback break generation bugs found by Andy Dyer
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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DTR_n <= MCR(4) or not MCR(0);
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DTR_n <= MCR(4) or not MCR(0);
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RTS_n <= MCR(4) or not MCR(1);
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RTS_n <= MCR(4) or not MCR(1);
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OUT1_n <= MCR(4) or not MCR(2);
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OUT1_n <= MCR(4) or not MCR(2);
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OUT2_n <= MCR(4) or not MCR(3);
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OUT2_n <= MCR(4) or not MCR(3);
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SOut <= (MCR(4) or TXD) and not LCR(6);
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SOut <= MCR(4) or (TXD and not LCR(6));
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RXD <= SIn when MCR(4) = '0' else TXD;
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RXD <= SIn when MCR(4) = '0' else (TXD and not LCR(6));
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Intr <= not IIR(0);
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Intr <= not IIR(0);
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-- Registers
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-- Registers
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DM0 <= DLL when LCR(7) = '1' else RBR;
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DM0 <= DLL when LCR(7) = '1' else RBR;
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