| Line 1... |
Line 1... |
--
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--
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-- Z80 compatible microprocessor core
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-- Z80 compatible microprocessor core
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--
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--
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-- Version : 0232
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-- Version : 0235
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--
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 54... |
Line 54... |
-- 0211 : Fixed Refresh addition and IM 1
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-- 0211 : Fixed Refresh addition and IM 1
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--
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--
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-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
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-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
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--
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--
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-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
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-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
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--
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-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.T80_Pack.all;
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use work.T80_Pack.all;
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| Line 67... |
Line 70... |
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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);
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);
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port(
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port(
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RESET_n : in std_logic;
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RESET_n : in std_logic;
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CLK_n : in std_logic;
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CLK_n : in std_logic;
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CEN : in std_logic;
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WAIT_n : in std_logic;
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WAIT_n : in std_logic;
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INT_n : in std_logic;
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INT_n : in std_logic;
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NMI_n : in std_logic;
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NMI_n : in std_logic;
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BUSRQ_n : in std_logic;
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BUSRQ_n : in std_logic;
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M1_n : out std_logic;
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M1_n : out std_logic;
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| Line 310... |
Line 314... |
AALU_OP_r <= "000";
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AALU_OP_r <= "000";
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XY_Ind <= '0';
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XY_Ind <= '0';
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elsif CLK_n'event and CLK_n = '1' then
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elsif CLK_n'event and CLK_n = '1' then
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if CEN = '1' then
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Arith16_r <= '0';
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Arith16_r <= '0';
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ALU_Op_r <= "0000";
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ALU_Op_r <= "0000";
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Rot_Op_r <= '0';
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Rot_Op_r <= '0';
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Bit_Op_r <= "00";
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Bit_Op_r <= "00";
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Save_ALU_r <= '0';
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Save_ALU_r <= '0';
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| Line 401... |
Line 407... |
A <= TmpAddr;
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A <= TmpAddr;
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PC <= unsigned(TmpAddr);
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PC <= unsigned(TmpAddr);
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elsif MCycle = MCycles and NMICycle = '1' then
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elsif MCycle = MCycles and NMICycle = '1' then
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A <= "0000000001100110";
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A <= "0000000001100110";
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PC <= "0000000001100110";
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PC <= "0000000001100110";
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elsif MCycle = MCycles and IntCycle = '1' and IStatus = "10" then
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elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
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A(15 downto 8) <= I;
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A(15 downto 8) <= I;
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A(7 downto 1) <= TmpAddr(7 downto 1);
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A(7 downto 0) <= TmpAddr(7 downto 0);
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A(0) <= '0';
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PC(15 downto 8) <= unsigned(I);
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PC(15 downto 8) <= unsigned(I);
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PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
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PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
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else
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else
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case Set_Addr_To is
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case Set_Addr_To is
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when aXY =>
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when aXY =>
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| Line 752... |
Line 757... |
end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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--
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--
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-- Buses
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-- Buses
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--
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--
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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process (CLK_n)
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process (CLK_n)
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begin
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begin
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if CLK_n'event and CLK_n = '1' then
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if CLK_n'event and CLK_n = '1' then
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if CEN = '1' then
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case Set_BusB_To is
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case Set_BusB_To is
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when "0111" =>
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when "0111" =>
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BusB <= ACC;
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BusB <= ACC;
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when "0000" =>
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when "0000" =>
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BusB <= B;
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BusB <= B;
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| Line 869... |
Line 877... |
when others =>
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when others =>
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BusB <= "--------";
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BusB <= "--------";
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end case;
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end case;
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end if;
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end if;
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end if;
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end process;
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end process;
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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--
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--
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-- Generate external control signals
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-- Generate external control signals
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| Line 882... |
Line 891... |
process (RESET_n,CLK_n)
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process (RESET_n,CLK_n)
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begin
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begin
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if RESET_n = '0' then
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if RESET_n = '0' then
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RFSH_n <= '1';
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RFSH_n <= '1';
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elsif CLK_n'event and CLK_n = '1' then
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elsif CLK_n'event and CLK_n = '1' then
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if CEN = '1' then
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if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
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if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
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RFSH_n <= '0';
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RFSH_n <= '0';
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else
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else
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RFSH_n <= '1';
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RFSH_n <= '1';
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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MC <= std_logic_vector(MCycle);
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MC <= std_logic_vector(MCycle);
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TS <= std_logic_vector(TState);
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TS <= std_logic_vector(TState);
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DI_Reg <= DI;
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DI_Reg <= DI;
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| Line 902... |
Line 913... |
process (RESET_n,CLK_n)
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process (RESET_n,CLK_n)
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begin
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begin
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if RESET_n = '0' then
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if RESET_n = '0' then
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M1_n <= '0';
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M1_n <= '0';
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elsif CLK_n'event and CLK_n = '1' then
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elsif CLK_n'event and CLK_n = '1' then
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if CEN = '1' then
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if T_Res = '1' and (MCycle = MCycles or (MCycle = "010" and I_DJNZ = '1' and B = "00000000")) then
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if T_Res = '1' and (MCycle = MCycles or (MCycle = "010" and I_DJNZ = '1' and B = "00000000")) then
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M1_n <= '0';
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M1_n <= '0';
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end if;
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end if;
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if MCycle = "001" and TState = 2 and Wait_n = '1' then
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if MCycle = "001" and TState = 2 and Wait_n = '1' then
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M1_n <= '1';
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M1_n <= '1';
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-------------------------------------------------------------------------
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-------------------------------------------------------------------------
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--
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--
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-- Syncronise inputs
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-- Syncronise inputs
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| Line 924... |
Line 937... |
if RESET_n = '0' then
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if RESET_n = '0' then
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INT_s <= '0';
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INT_s <= '0';
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NMI_s <= '0';
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NMI_s <= '0';
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OldNMI_n := '0';
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OldNMI_n := '0';
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elsif CLK_n'event and CLK_n = '1' then
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elsif CLK_n'event and CLK_n = '1' then
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if CEN = '1' then
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INT_s <= not INT_n;
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INT_s <= not INT_n;
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if NMICycle = '1' then
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if NMICycle = '1' then
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NMI_s <= '0';
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NMI_s <= '0';
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elsif NMI_n = '0' and OldNMI_n = '1' then
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elsif NMI_n = '0' and OldNMI_n = '1' then
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NMI_s <= '1';
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NMI_s <= '1';
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end if;
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end if;
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OldNMI_n := NMI_n;
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OldNMI_n := NMI_n;
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end if;
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end if;
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end if;
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end process;
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end process;
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-------------------------------------------------------------------------
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-------------------------------------------------------------------------
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--
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--
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-- Main state machine
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-- Main state machine
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| Line 953... |
Line 968... |
IntCycle <= '0';
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IntCycle <= '0';
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XY_Fetch <= '0';
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XY_Fetch <= '0';
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IntE_FF1 <= '0';
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IntE_FF1 <= '0';
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IntE_FF2 <= '0';
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IntE_FF2 <= '0';
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elsif CLK_n'event and CLK_n = '1' then -- CLK_n is the clock signal
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elsif CLK_n'event and CLK_n = '1' then -- CLK_n is the clock signal
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if CEN = '1' then
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if TState = 2 then
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if TState = 2 then
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if SetEI = '1' then
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if SetEI = '1' then
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IntE_FF1 <= '1';
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IntE_FF1 <= '1';
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IntE_FF2 <= '1';
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IntE_FF2 <= '1';
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end if;
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end if;
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| Line 1011... |
Line 1027... |
else
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else
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TState <= TState + 1;
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TState <= TState + 1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end;
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end;
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No newline at end of file
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No newline at end of file
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