| Line 1... |
Line 1... |
--
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--
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-- Z80 compatible microprocessor core
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-- Z80 compatible microprocessor core
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--
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--
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-- Version : 0237
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-- Version : 0238
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--
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 59... |
Line 59... |
--
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--
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-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
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-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
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--
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--
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-- 0237 : Changed 8080 I/O address output, added IntE output
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-- 0237 : Changed 8080 I/O address output, added IntE output
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--
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--
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-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.T80_Pack.all;
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use work.T80_Pack.all;
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| Line 79... |
Line 81... |
INT_n : in std_logic;
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INT_n : in std_logic;
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NMI_n : in std_logic;
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NMI_n : in std_logic;
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BUSRQ_n : in std_logic;
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BUSRQ_n : in std_logic;
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M1_n : out std_logic;
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M1_n : out std_logic;
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IORQ : out std_logic;
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IORQ : out std_logic;
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NoRead : out std_logic;
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Write : out std_logic;
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Write : out std_logic;
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RFSH_n : out std_logic;
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RFSH_n : out std_logic;
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HALT_n : out std_logic;
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HALT_n : out std_logic;
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BUSAK_n : out std_logic;
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BUSAK_n : out std_logic;
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A : out std_logic_vector(15 downto 0);
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A : out std_logic_vector(15 downto 0);
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| Line 132... |
Line 135... |
signal IStatus : std_logic_vector(1 downto 0);
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signal IStatus : std_logic_vector(1 downto 0);
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signal DI_Reg : std_logic_vector(7 downto 0);
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signal DI_Reg : std_logic_vector(7 downto 0);
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signal T_Res : std_logic;
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signal T_Res : std_logic;
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signal XY_State : std_logic_vector(1 downto 0);
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signal XY_State : std_logic_vector(1 downto 0);
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signal XY_Fetch : std_logic;
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signal XY_Fetch : std_logic_vector(1 downto 0);
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signal NextIs_XY_Fetch : std_logic;
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signal NextIs_XY_Fetch : std_logic;
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signal XY_Ind : std_logic;
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signal XY_Ind : std_logic;
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-- ALU signals
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-- ALU signals
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signal BusB : std_logic_vector(7 downto 0);
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signal BusB : std_logic_vector(7 downto 0);
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| Line 146... |
Line 149... |
signal F_Save : std_logic_vector(7 downto 0);
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signal F_Save : std_logic_vector(7 downto 0);
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-- Registered micro code outputs
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-- Registered micro code outputs
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signal Read_To_Reg_r : std_logic_vector(4 downto 0);
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signal Read_To_Reg_r : std_logic_vector(4 downto 0);
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signal Arith16_r : std_logic;
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signal Arith16_r : std_logic;
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signal Z16_r : std_logic;
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signal ALU_Op_r : std_logic_vector(3 downto 0);
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signal ALU_Op_r : std_logic_vector(3 downto 0);
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signal AALU_OP_r : std_logic_vector(2 downto 0);
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signal AALU_OP_r : std_logic_vector(2 downto 0);
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signal Rot_Op_r : std_logic;
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signal Rot_Op_r : std_logic;
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signal Bit_Op_r : std_logic_vector(1 downto 0);
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signal Bit_Op_r : std_logic_vector(1 downto 0);
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signal Save_ALU_r : std_logic;
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signal Save_ALU_r : std_logic;
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| Line 263... |
Line 267... |
I_INRC => I_INRC,
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I_INRC => I_INRC,
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SetDI => SetDI,
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SetDI => SetDI,
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SetEI => SetEI,
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SetEI => SetEI,
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IMode => IMode,
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IMode => IMode,
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Halt => Halt,
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Halt => Halt,
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NoRead => NoRead,
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Write => Write);
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Write => Write);
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alu : T80_ALU
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alu : T80_ALU
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port map(
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port map(
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Arith16 => Arith16_r,
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Arith16 => Arith16_r,
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Z16 => Z16_r,
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ALU_Op => ALU_Op_r,
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ALU_Op => ALU_Op_r,
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Rot_Op => Rot_Op_r,
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Rot_Op => Rot_Op_r,
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Bit_Op => Bit_Op_r,
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Bit_Op => Bit_Op_r,
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IR => IR,
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IR => IR,
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ISet => ISet,
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ISet => ISet,
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| Line 280... |
Line 286... |
F_In => F,
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F_In => F,
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Q => ALU_Q,
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Q => ALU_Q,
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F_Out => F_Out,
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F_Out => F_Out,
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F_Save => F_Save);
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F_Save => F_Save);
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T_Res <= '1' when (TState = unsigned(TStates) and XY_Fetch = '0') or
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T_Res <= '1' when (TState = unsigned(TStates) and XY_Fetch(0) = '0') or
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(XY_Fetch = '1' and TState = 4) else '0'; -- Incorrect, should be 8 !!!!!!!!!!!!!!!!
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(XY_Fetch(0) = '1' and TState = "111" and Mode = 0) or
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(XY_Fetch(0) = '1' and TState = "100" and Mode = 1) else '0';
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NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and ((Set_Addr_To = aXY and IR /= "11001011") or
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NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and ((Set_Addr_To = aXY and IR /= "11001011") or
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(MCycle = "001" and IR = "11001011") or
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(MCycle = "001" and IR = "11001011") or
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(MCycle = "001" and IR = "00110110")) else '0';
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(MCycle = "001" and IR = "00110110")) else '0';
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| Line 309... |
Line 316... |
R <= (others => '0');
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R <= (others => '0');
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SP <= (others => '1');
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SP <= (others => '1');
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Read_To_Reg_r <= "00000";
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Read_To_Reg_r <= "00000";
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Arith16_r <= '0';
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Arith16_r <= '0';
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Z16_r <= '0';
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ALU_Op_r <= "0000";
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ALU_Op_r <= "0000";
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Rot_Op_r <= '0';
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Rot_Op_r <= '0';
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Bit_Op_r <= "00";
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Bit_Op_r <= "00";
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Save_ALU_r <= '0';
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Save_ALU_r <= '0';
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PreserveC_r <= '0';
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PreserveC_r <= '0';
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| Line 321... |
Line 329... |
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elsif CLK_n'event and CLK_n = '1' then
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elsif CLK_n'event and CLK_n = '1' then
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if CEN = '1' then
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if CEN = '1' then
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Arith16_r <= '0';
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ALU_Op_r <= "0000";
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ALU_Op_r <= "0000";
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Rot_Op_r <= '0';
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Rot_Op_r <= '0';
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Bit_Op_r <= "00";
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Bit_Op_r <= "00";
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Save_ALU_r <= '0';
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Save_ALU_r <= '0';
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PreserveC_r <= '0';
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AALU_OP_r <= "000";
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AALU_OP_r <= "000";
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Read_To_Reg_r <= "00000";
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Read_To_Reg_r <= "00000";
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MCycles <= MCycles_d;
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MCycles <= MCycles_d;
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if IMode /= "11" then
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if IMode /= "11" then
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IStatus <= IMode;
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IStatus <= IMode;
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end if;
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end if;
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if MCycle = "001" and TState(2) = '0' and XY_Fetch = '0' then
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Arith16_r <= Arith16;
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PreserveC_r <= PreserveC;
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if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
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Z16_r <= '1';
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else
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Z16_r <= '0';
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end if;
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if MCycle = "001" and TState(2) = '0' and XY_Fetch(0) = '0' then
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-- MCycle = 1 and TState = 1, 2, or 3
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-- MCycle = 1 and TState = 1, 2, or 3
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if TState = 2 and Wait_n = '1' then
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if TState = 2 and Wait_n = '1' then
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if Mode < 2 then
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if Mode < 2 then
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A(7 downto 0) <= std_logic_vector(R);
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A(7 downto 0) <= std_logic_vector(R);
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| Line 382... |
Line 396... |
end if;
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end if;
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else
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else
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-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
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-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
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if XY_Fetch = '1' then
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if XY_Fetch(0) = '1' then
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XY_Ind <= '1';
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XY_Ind <= '1';
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end if;
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end if;
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if T_Res = '1' then
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if T_Res = '1' then
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if Jump = '1' then
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if Jump = '1' then
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| Line 458... |
Line 472... |
when aNone =>
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when aNone =>
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A <= std_logic_vector(PC);
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A <= std_logic_vector(PC);
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end case;
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end case;
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end if;
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end if;
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Arith16_r <= Arith16;
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Save_ALU_r <= Save_ALU;
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ALU_Op_r <= ALU_Op;
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ALU_Op_r <= ALU_Op;
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Rot_Op_r <= Rot_Op;
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Rot_Op_r <= Rot_Op;
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Bit_Op_r <= Bit_Op;
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Bit_Op_r <= Bit_Op;
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Save_ALU_r <= Save_ALU;
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PreserveC_r <= PreserveC;
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if Save_ALU = '1' then
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if Save_ALU = '1' then
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if Rot_Op = '0' and Bit_Op = "00" then
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if Rot_Op = '0' and Bit_Op = "00" then
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if ALU_Op(3) = '1' then
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if ALU_Op(3) = '1' then
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AALU_OP_r <= ALU_Op(2 downto 0);
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AALU_OP_r <= ALU_Op(2 downto 0);
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else
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else
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| Line 503... |
Line 515... |
end if;
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end if;
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if TState = 2 and Wait_n = '1' then
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if TState = 2 and Wait_n = '1' then
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if JumpE = '1' then
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if JumpE = '1' then
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PC <= unsigned(signed(PC) + signed(DI_Reg));
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PC <= unsigned(signed(PC) + signed(DI_Reg));
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elsif Inc_PC = '1' or XY_Fetch = '1' then
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elsif Inc_PC = '1' or XY_Fetch(0) = '1' then
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PC <= PC + 1;
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PC <= PC + 1;
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end if;
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end if;
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if I_BTR = '1' then
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if I_BTR = '1' then
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PC <= PC - 2;
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PC <= PC - 2;
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end if;
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end if;
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if RstP = '1' then
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if RstP = '1' then
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TmpAddr <= (others =>'0');
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TmpAddr <= (others =>'0');
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TmpAddr(5 downto 3) <= IR(5 downto 3);
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TmpAddr(5 downto 3) <= IR(5 downto 3);
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end if;
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end if;
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end if;
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end if;
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if TState = 3 and XY_Fetch = '1' then
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if TState = 3 and XY_Fetch = "01" then
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if XY_State = "01" then
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if XY_State = "01" then
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TmpAddr <= std_logic_vector(signed(IX) + signed(DI_Reg));
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TmpAddr <= std_logic_vector(signed(IX) + signed(DI_Reg));
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end if;
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end if;
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if XY_State = "10" then
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if XY_State = "10" then
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TmpAddr <= std_logic_vector(signed(IY) + signed(DI_Reg));
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TmpAddr <= std_logic_vector(signed(IY) + signed(DI_Reg));
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| Line 915... |
Line 927... |
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MC <= std_logic_vector(MCycle);
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MC <= std_logic_vector(MCycle);
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TS <= std_logic_vector(TState);
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TS <= std_logic_vector(TState);
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DI_Reg <= DI;
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DI_Reg <= DI;
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HALT_n <= not Halt_FF;
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HALT_n <= not Halt_FF;
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False_M1 <= XY_Fetch;
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False_M1 <= XY_Fetch(0);
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IntCycle_n <= not IntCycle;
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IntCycle_n <= not IntCycle;
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process (RESET_n,CLK_n)
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process (RESET_n,CLK_n)
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begin
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begin
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if RESET_n = '0' then
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if RESET_n = '0' then
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| Line 974... |
Line 986... |
BReq_FF <= '0';
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BReq_FF <= '0';
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Halt_FF <= '0';
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Halt_FF <= '0';
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BUSAK_n <= '1';
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BUSAK_n <= '1';
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NMICycle <= '0';
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NMICycle <= '0';
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IntCycle <= '0';
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IntCycle <= '0';
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XY_Fetch <= '0';
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XY_Fetch <= "00";
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IntE_FF1 <= '0';
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IntE_FF1 <= '0';
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IntE_FF2 <= '0';
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IntE_FF2 <= '0';
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elsif CLK_n'event and CLK_n = '1' then -- CLK_n is the clock signal
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elsif CLK_n'event and CLK_n = '1' then -- CLK_n is the clock signal
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if CEN = '1' then
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if CEN = '1' then
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if TState = 2 then
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if TState = 2 then
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| Line 1004... |
Line 1016... |
BReq_FF <= '0';
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BReq_FF <= '0';
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BUSAK_n <= '1';
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BUSAK_n <= '1';
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end if;
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end if;
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else
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else
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if TState = 2 and Wait_n = '0' then
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if TState = 2 and Wait_n = '0' then
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elsif XY_Fetch = "01" and TState = "100" and Mode = 0 then
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XY_Fetch <= "11";
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TState <= "011";
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elsif T_Res = '1' then
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elsif T_Res = '1' then
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if Halt = '1' then
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if Halt = '1' then
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Halt_FF <= '1';
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Halt_FF <= '1';
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end if;
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end if;
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if BUSRQ_n = '0' then
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if BUSRQ_n = '0' then
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BReq_FF <= '1';
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BReq_FF <= '1';
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BUSAK_n <= '0';
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BUSAK_n <= '0';
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else
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else
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TState <= "001";
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TState <= "001";
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XY_Fetch <= '0';
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XY_Fetch <= "00";
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if NextIs_XY_Fetch = '1' then
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if NextIs_XY_Fetch = '1' then
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XY_Fetch <= '1';
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XY_Fetch <= "01";
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elsif MCycle = MCycles or (MCycle = "010" and I_DJNZ = '1' and B = "00000000") then
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elsif MCycle = MCycles or (MCycle = "010" and I_DJNZ = '1' and B = "00000000") then
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MCycle <= "001";
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MCycle <= "001";
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IntCycle <= '0';
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IntCycle <= '0';
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NMICycle <= '0';
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NMICycle <= '0';
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if NMI_s = '1' and Prefix = "00" then
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if NMI_s = '1' and Prefix = "00" then
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