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Line 1... |
--
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--
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-- Z80 compatible microprocessor core
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-- Z80 compatible microprocessor core
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--
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--
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-- Version : 0242
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-- Version : 0247
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--
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 62... |
Line 62... |
--
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--
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-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
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-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
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--
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--
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-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
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-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
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--
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--
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-- 0247 : Fixed bus req/ack cycle
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.T80_Pack.all;
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use work.T80_Pack.all;
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| Line 149... |
Line 151... |
signal ID16 : signed(15 downto 0);
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signal ID16 : signed(15 downto 0);
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signal Save_Mux : std_logic_vector(7 downto 0);
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signal Save_Mux : std_logic_vector(7 downto 0);
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signal TState : unsigned(2 downto 0);
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signal TState : unsigned(2 downto 0);
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signal MCycle : std_logic_vector(2 downto 0);
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signal MCycle : std_logic_vector(2 downto 0);
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signal BReq_FF : std_logic;
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signal IntE_FF1 : std_logic;
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signal IntE_FF1 : std_logic;
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signal IntE_FF2 : std_logic;
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signal IntE_FF2 : std_logic;
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signal Halt_FF : std_logic;
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signal Halt_FF : std_logic;
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signal BusReq_s : std_logic;
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signal BusAck : std_logic;
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signal ClkEn : std_logic;
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signal NMI_s : std_logic;
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signal NMI_s : std_logic;
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signal INT_s : std_logic;
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signal INT_s : std_logic;
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signal IStatus : std_logic_vector(1 downto 0);
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signal IStatus : std_logic_vector(1 downto 0);
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signal DI_Reg : std_logic_vector(7 downto 0);
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signal DI_Reg : std_logic_vector(7 downto 0);
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| Line 323... |
Line 327... |
BusB => BusB,
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BusB => BusB,
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F_In => F,
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F_In => F,
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Q => ALU_Q,
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Q => ALU_Q,
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F_Out => F_Out);
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F_Out => F_Out);
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ClkEn <= CEN and not BusAck;
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T_Res <= '1' when TState = unsigned(TStates) else '0';
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T_Res <= '1' when TState = unsigned(TStates) else '0';
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NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
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NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
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((Set_Addr_To = aXY) or
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((Set_Addr_To = aXY) or
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(MCycle = "001" and IR = "11001011") or
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(MCycle = "001" and IR = "11001011") or
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| Line 368... |
Line 374... |
PreserveC_r <= '0';
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PreserveC_r <= '0';
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XY_Ind <= '0';
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XY_Ind <= '0';
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elsif CLK_n'event and CLK_n = '1' then
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elsif CLK_n'event and CLK_n = '1' then
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if CEN = '1' then
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if ClkEn = '1' then
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ALU_Op_r <= "0000";
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ALU_Op_r <= "0000";
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Save_ALU_r <= '0';
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Save_ALU_r <= '0';
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Read_To_Reg_r <= "00000";
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Read_To_Reg_r <= "00000";
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| Line 697... |
Line 703... |
--
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--
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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process (CLK_n)
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process (CLK_n)
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begin
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begin
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if CLK_n'event and CLK_n = '1' then
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if CLK_n'event and CLK_n = '1' then
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if CEN = '1' then
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if ClkEn = '1' then
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-- Bus A / Write
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-- Bus A / Write
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RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
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RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
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if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
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if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
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RegAddrA_r <= XY_State(1) & "11";
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RegAddrA_r <= XY_State(1) & "11";
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end if;
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end if;
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| Line 811... |
Line 817... |
end process;
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end process;
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Regs : T80_Reg
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Regs : T80_Reg
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port map(
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port map(
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Clk => CLK_n,
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Clk => CLK_n,
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CEN => CEN,
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CEN => ClkEn,
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WEH => RegWEH,
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WEH => RegWEH,
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WEL => RegWEL,
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WEL => RegWEL,
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AddrA => RegAddrA,
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AddrA => RegAddrA,
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AddrB => RegAddrB,
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AddrB => RegAddrB,
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AddrC => RegAddrC,
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AddrC => RegAddrC,
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| Line 834... |
Line 840... |
--
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--
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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process (CLK_n)
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process (CLK_n)
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begin
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begin
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if CLK_n'event and CLK_n = '1' then
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if CLK_n'event and CLK_n = '1' then
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if CEN = '1' then
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if ClkEn = '1' then
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case Set_BusB_To is
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case Set_BusB_To is
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when "0111" =>
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when "0111" =>
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BusB <= ACC;
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BusB <= ACC;
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when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
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when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
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if Set_BusB_To(0) = '1' then
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if Set_BusB_To(0) = '1' then
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| Line 912... |
Line 918... |
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MC <= std_logic_vector(MCycle);
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MC <= std_logic_vector(MCycle);
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TS <= std_logic_vector(TState);
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TS <= std_logic_vector(TState);
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DI_Reg <= DI;
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DI_Reg <= DI;
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HALT_n <= not Halt_FF;
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HALT_n <= not Halt_FF;
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BUSAK_n <= not BusAck;
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IntCycle_n <= not IntCycle;
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IntCycle_n <= not IntCycle;
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IntE <= IntE_FF1;
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IntE <= IntE_FF1;
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IORQ <= IORQ_i;
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IORQ <= IORQ_i;
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Stop <= I_DJNZ;
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Stop <= I_DJNZ;
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| Line 926... |
Line 933... |
-------------------------------------------------------------------------
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-------------------------------------------------------------------------
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process (RESET_n, CLK_n)
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process (RESET_n, CLK_n)
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variable OldNMI_n : std_logic;
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variable OldNMI_n : std_logic;
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begin
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begin
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if RESET_n = '0' then
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if RESET_n = '0' then
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BusReq_s <= '0';
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INT_s <= '0';
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INT_s <= '0';
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NMI_s <= '0';
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NMI_s <= '0';
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OldNMI_n := '0';
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OldNMI_n := '0';
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elsif CLK_n'event and CLK_n = '1' then
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elsif CLK_n'event and CLK_n = '1' then
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if CEN = '1' then
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if CEN = '1' then
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BusReq_s <= not BUSRQ_n;
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INT_s <= not INT_n;
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INT_s <= not INT_n;
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if NMICycle = '1' then
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if NMICycle = '1' then
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NMI_s <= '0';
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NMI_s <= '0';
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elsif NMI_n = '0' and OldNMI_n = '1' then
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elsif NMI_n = '0' and OldNMI_n = '1' then
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NMI_s <= '1';
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NMI_s <= '1';
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| Line 953... |
Line 962... |
begin
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begin
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if RESET_n = '0' then
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if RESET_n = '0' then
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MCycle <= "001";
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MCycle <= "001";
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TState <= "000";
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TState <= "000";
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Pre_XY_F_M <= "000";
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Pre_XY_F_M <= "000";
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BReq_FF <= '0';
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Halt_FF <= '0';
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Halt_FF <= '0';
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BUSAK_n <= '1';
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BusAck <= '0';
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NMICycle <= '0';
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NMICycle <= '0';
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IntCycle <= '0';
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IntCycle <= '0';
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IntE_FF1 <= '0';
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IntE_FF1 <= '0';
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IntE_FF2 <= '0';
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IntE_FF2 <= '0';
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No_BTR <= '0';
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No_BTR <= '0';
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Auto_Wait_t1 <= '0';
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Auto_Wait_t1 <= '0';
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Auto_Wait_t2 <= '0';
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Auto_Wait_t2 <= '0';
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M1_n <= '1';
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M1_n <= '1';
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elsif CLK_n'event and CLK_n = '1' then -- CLK_n is the clock signal
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elsif CLK_n'event and CLK_n = '1' then
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if CEN = '1' then
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if CEN = '1' then
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if T_Res = '1' then
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if T_Res = '1' then
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Auto_Wait_t1 <= '0';
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Auto_Wait_t1 <= '0';
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else
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else
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Auto_Wait_t1 <= Auto_Wait or IORQ_i;
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Auto_Wait_t1 <= Auto_Wait or IORQ_i;
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| Line 996... |
Line 1004... |
Halt_FF <= '0';
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Halt_FF <= '0';
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end if;
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end if;
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if MCycle = "001" and TState = 2 and Wait_n = '1' then
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if MCycle = "001" and TState = 2 and Wait_n = '1' then
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M1_n <= '1';
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M1_n <= '1';
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end if;
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end if;
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if BReq_FF = '1' then
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if BusReq_s = '1' and BusAck = '1' then
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if BUSRQ_n = '1' then
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BReq_FF <= '0';
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BUSAK_n <= '1';
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end if;
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else
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else
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BusAck <= '0';
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if TState = 2 and Wait_n = '0' then
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if TState = 2 and Wait_n = '0' then
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elsif T_Res = '1' then
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elsif T_Res = '1' then
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if Halt = '1' then
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if Halt = '1' then
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Halt_FF <= '1';
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Halt_FF <= '1';
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end if;
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end if;
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if BUSRQ_n = '0' then
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if BusReq_s = '1' then
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BReq_FF <= '1';
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BusAck <= '1';
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BUSAK_n <= '0';
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else
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else
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TState <= "001";
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TState <= "001";
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if NextIs_XY_Fetch = '1' then
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if NextIs_XY_Fetch = '1' then
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MCycle <= "110";
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MCycle <= "110";
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Pre_XY_F_M <= MCycle;
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Pre_XY_F_M <= MCycle;
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