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Line 1... |
--
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--
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-- Z80 compatible microprocessor core
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-- Z80 compatible microprocessor core
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--
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--
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-- Version : 0214
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-- Version : 0232
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--
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (dwallner@hem2.passagen.se)
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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| Line 36... |
Line 36... |
-- Please report bugs to the author, but before you do so, please
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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-- you have the latest version of this file.
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--
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--
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-- The latest version of this file can be found at:
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-- The latest version of this file can be found at:
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-- http://hem.passagen.se/dwallner/vhdl.html
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-- http://www.opencores.org/cvsweb.shtml/t80/
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--
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--
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-- Limitations :
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-- Limitations :
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-- No extra I/O waitstate
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-- No extra I/O waitstate
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-- GB instruction set is incomplete
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-- GB instruction set is incomplete
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-- Not all instruction timing are correct
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-- Not all instruction timing are correct
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| Line 53... |
Line 53... |
--
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--
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-- 0211 : Fixed Refresh addition and IM 1
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-- 0211 : Fixed Refresh addition and IM 1
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--
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--
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-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
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-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
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--
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--
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-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.T80_Pack.all;
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use work.T80_Pack.all;
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if MCycle = "001" and TState(2) = '0' and XY_Fetch = '0' then
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if MCycle = "001" and TState(2) = '0' and XY_Fetch = '0' then
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-- MCycle = 1 and TState = 1, 2, or 3
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-- MCycle = 1 and TState = 1, 2, or 3
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if TState = 2 and Wait_n = '1' then
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if TState = 2 and Wait_n = '1' then
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if Mode < 2 then
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A(7 downto 0) <= std_logic_vector(R);
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A(7 downto 0) <= std_logic_vector(R);
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A(15 downto 8) <= I;
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A(15 downto 8) <= I;
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R(6 downto 0) <= R(6 downto 0) + 1;
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R(6 downto 0) <= R(6 downto 0) + 1;
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end if;
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if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
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if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
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PC <= PC + 1;
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PC <= PC + 1;
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end if;
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end if;
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process (RESET_n,CLK_n)
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process (RESET_n,CLK_n)
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begin
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begin
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if RESET_n = '0' then
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if RESET_n = '0' then
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M1_n <= '0';
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M1_n <= '0';
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elsif CLK_n'event and CLK_n = '1' then
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elsif CLK_n'event and CLK_n = '1' then
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if T_Res = '1' and MCycle = MCycles then
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if T_Res = '1' and (MCycle = MCycles or (MCycle = "010" and I_DJNZ = '1' and B = "00000000")) then
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M1_n <= '0';
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M1_n <= '0';
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end if;
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end if;
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if MCycle = "001" and TState = 2 and Wait_n = '1' then
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if MCycle = "001" and TState = 2 and Wait_n = '1' then
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M1_n <= '1';
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M1_n <= '1';
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end if;
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end if;
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