Subversion Repositories t80

--

--

-- 8080 compatible microprocessor core, synchronous top level with clock enable

-- 8080 compatible microprocessor core, synchronous top level with clock enable

-- Different timing than the original 8080

-- Different timing than the original 8080

-- Inputs needs to be synchronous and outputs may glitch

-- Inputs needs to be synchronous and outputs may glitch

--

--

--

--

-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)

-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)

--

--

-- All rights reserved

-- All rights reserved

--

--

--

--

--      0238 : Updated for T80 interface change

--      0238 : Updated for T80 interface change

--

--

--      0240 : Updated for T80 interface change

--      0240 : Updated for T80 interface change

--

--

library IEEE;

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use IEEE.numeric_std.all;

use work.T80_Pack.all;

use work.T80_Pack.all;

        DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);   -- INP

        DO(6) <= IORQ and not Write when TState = "001" else DO_i(6);   -- INP

        DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);        -- MEMR

        DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7);        -- MEMR

        u0 : T80

        u0 : T80

                generic map(

                generic map(

                port map(

                port map(

                        CEN => CLKEN,

                        CEN => CLKEN,

                        M1_n => open,

                        M1_n => open,

                        IORQ => IORQ,

                        IORQ => IORQ,

                        NoRead => NoRead,

                        NoRead => NoRead,