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Line 1... |
--
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--
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-- Z80 compatible microprocessor core
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-- Z80 compatible microprocessor core
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--
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--
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-- Version : 0214
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-- Version : 0235
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--
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (dwallner@hem2.passagen.se)
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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| Line 36... |
Line 36... |
-- Please report bugs to the author, but before you do so, please
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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-- you have the latest version of this file.
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--
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--
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-- The latest version of this file can be found at:
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-- The latest version of this file can be found at:
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-- http://hem.passagen.se/dwallner/vhdl.html
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-- http://www.opencores.org/cvsweb.shtml/t80/
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--
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--
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-- Limitations :
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-- Limitations :
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--
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--
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-- File history :
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-- File history :
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--
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--
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| Line 48... |
Line 48... |
--
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--
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-- 0211 : Fixed IM 1
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-- 0211 : Fixed IM 1
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--
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--
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-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
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-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
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--
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--
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-- 0235 : Added IM 2 fix by Mike Johnson
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.T80_Pack.all;
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use work.T80_Pack.all;
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| Line 661... |
Line 663... |
Write <= '1';
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Write <= '1';
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when others => null;
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when others => null;
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end case;
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end case;
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elsif IntCycle = '1' then
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elsif IntCycle = '1' then
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-- INT (IM 2)
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-- INT (IM 2)
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MCycles <= "011";
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MCycles <= "101";
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case to_integer(unsigned(MCycle)) is
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case to_integer(unsigned(MCycle)) is
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when 1 =>
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when 1 =>
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LDZ <= '1';
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LDZ <= '1';
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TStates <= "101";
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TStates <= "101";
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IncDec_16 <= "1111";
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IncDec_16 <= "1111";
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| Line 678... |
Line 680... |
Set_Addr_To <= aSP;
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Set_Addr_To <= aSP;
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Set_BusB_To <= "1100";
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Set_BusB_To <= "1100";
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when 3 =>
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when 3 =>
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TStates <= "100";
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TStates <= "100";
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Write <= '1';
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Write <= '1';
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when 4 =>
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Inc_PC <= '1';
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LDZ <= '1';
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when 5 =>
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Jump <= '1';
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when others => null;
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when others => null;
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end case;
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end case;
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else
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else
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-- NOP
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-- NOP
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end if;
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end if;
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