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[/] [t80/] [trunk/] [rtl/] [vhdl/] [T80_MCode.vhd] - Diff between revs 15 and 25

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Line 1... Line 1... 
--
 
--
 
-- Z80 compatible microprocessor core
 
-- Z80 compatible microprocessor core
 
--
 
--
 
-- Version : 0235
 
-- Version : 0238
 
--
 
--
 
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
 
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
 
--
 
--
 
-- All rights reserved
 
-- All rights reserved
 
--
 
--
Line 50... Line 50... 
--
 
--
 
--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
 
--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
 
--
 
--
 
--      0235 : Added IM 2 fix by Mike Johnson
 
--      0235 : Added IM 2 fix by Mike Johnson
 
--
 
--
 
 
 
--      0238 : Added NoRead signal
 
 
 
--
 
 
 
 
 
library IEEE;
 
library IEEE;
 
use IEEE.std_logic_1164.all;
 
use IEEE.std_logic_1164.all;
 
use IEEE.numeric_std.all;
 
use IEEE.numeric_std.all;
 
use work.T80_Pack.all;
 
use work.T80_Pack.all;
Line 114... Line 116... 
                I_INRC                  : out std_logic;
 
                I_INRC                  : out std_logic;
 
                SetDI                   : out std_logic;
 
                SetDI                   : out std_logic;
 
                SetEI                   : out std_logic;
 
                SetEI                   : out std_logic;
 
                IMode                   : out std_logic_vector(1 downto 0);
 
                IMode                   : out std_logic_vector(1 downto 0);
 
                Halt                    : out std_logic;
 
                Halt                    : out std_logic;
 
 
 
                NoRead                  : out std_logic;
 
                Write                   : out std_logic
 
                Write                   : out std_logic
 
        );
 
        );
 
end T80_MCode;
 
end T80_MCode;
 
 
 
 
 
architecture rtl of T80_MCode is
 
architecture rtl of T80_MCode is
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                I_INRC <= '0';
 
                I_INRC <= '0';
 
                SetDI <= '0';
 
                SetDI <= '0';
 
                SetEI <= '0';
 
                SetEI <= '0';
 
                IMode <= "11";
 
                IMode <= "11";
 
                Halt <= '0';
 
                Halt <= '0';
 
 
 
                NoRead <= '0';
 
                Write <= '0';
 
                Write <= '0';
 
 
 
 
 
                case ISet is
 
                case ISet is
 
                when "00" =>
 
                when "00" =>
 
 
 
 
Line 706... Line 710... 
                when "00001001"|"00011001"|"00101001"|"00111001" =>
 
                when "00001001"|"00011001"|"00101001"|"00111001" =>
 
                        -- ADD HL,ss
 
                        -- ADD HL,ss
 
                        MCycles <= "011";
 
                        MCycles <= "011";
 
                        case to_integer(unsigned(MCycle)) is
 
                        case to_integer(unsigned(MCycle)) is
 
                        when 2 =>
 
                        when 2 =>
 
 
 
                                NoRead <= '1';
 
                                ALU_Op <= "1000";
 
                                ALU_Op <= "1000";
 
                                Read_To_Reg <= '1';
 
                                Read_To_Reg <= '1';
 
                                Save_ALU <= '1';
 
                                Save_ALU <= '1';
 
                                Set_BusA_To(2 downto 0) <= "101";
 
                                Set_BusA_To(2 downto 0) <= "101";
 
                                case to_integer(unsigned(IR(5 downto 4))) is
 
                                case to_integer(unsigned(IR(5 downto 4))) is
Line 720... Line 725... 
                                        Set_BusB_To <= "1000";
 
                                        Set_BusB_To <= "1000";
 
                                end case;
 
                                end case;
 
                                TStates <= "100";
 
                                TStates <= "100";
 
                                Arith16 <= '1';
 
                                Arith16 <= '1';
 
                        when 3 =>
 
                        when 3 =>
 
 
 
                                NoRead <= '1';
 
                                Read_To_Reg <= '1';
 
                                Read_To_Reg <= '1';
 
                                Save_ALU <= '1';
 
                                Save_ALU <= '1';
 
                                ALU_Op <= "1001";
 
                                ALU_Op <= "1001";
 
                                Set_BusA_To(2 downto 0) <= "100";
 
                                Set_BusA_To(2 downto 0) <= "100";
 
                                case to_integer(unsigned(IR(5 downto 4))) is
 
                                case to_integer(unsigned(IR(5 downto 4))) is
Line 792... Line 798... 
                        MCycles <= "011";
 
                        MCycles <= "011";
 
                        case to_integer(unsigned(MCycle)) is
 
                        case to_integer(unsigned(MCycle)) is
 
                        when 2 =>
 
                        when 2 =>
 
                                Inc_PC <= '1';
 
                                Inc_PC <= '1';
 
                        when 3 =>
 
                        when 3 =>
 
 
 
                                NoRead <= '1';
 
                                JumpE <= '1';
 
                                JumpE <= '1';
 
                                TStates <= "101";
 
                                TStates <= "101";
 
                        when others => null;
 
                        when others => null;
 
                        end case;
 
                        end case;
 
                when "00111000" =>
 
                when "00111000" =>
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                                Inc_PC <= '1';
 
                                Inc_PC <= '1';
 
                                if F(0) = '0' then
 
                                if F(0) = '0' then
 
                                        MCycles <= "010";
 
                                        MCycles <= "010";
 
                                end if;
 
                                end if;
 
                        when 3 =>
 
                        when 3 =>
 
 
 
                                NoRead <= '1';
 
                                JumpE <= '1';
 
                                JumpE <= '1';
 
                                TStates <= "101";
 
                                TStates <= "101";
 
                        when others => null;
 
                        when others => null;
 
                        end case;
 
                        end case;
 
                when "00110000" =>
 
                when "00110000" =>
Line 820... Line 828... 
                                Inc_PC <= '1';
 
                                Inc_PC <= '1';
 
                                if F(0) = '1' then
 
                                if F(0) = '1' then
 
                                        MCycles <= "010";
 
                                        MCycles <= "010";
 
                                end if;
 
                                end if;
 
                        when 3 =>
 
                        when 3 =>
 
 
 
                                NoRead <= '1';
 
                                JumpE <= '1';
 
                                JumpE <= '1';
 
                                TStates <= "101";
 
                                TStates <= "101";
 
                        when others => null;
 
                        when others => null;
 
                        end case;
 
                        end case;
 
                when "00101000" =>
 
                when "00101000" =>
Line 834... Line 843... 
                                Inc_PC <= '1';
 
                                Inc_PC <= '1';
 
                                if F(6) = '0' then
 
                                if F(6) = '0' then
 
                                        MCycles <= "010";
 
                                        MCycles <= "010";
 
                                end if;
 
                                end if;
 
                        when 3 =>
 
                        when 3 =>
 
 
 
                                NoRead <= '1';
 
                                JumpE <= '1';
 
                                JumpE <= '1';
 
                                TStates <= "101";
 
                                TStates <= "101";
 
                        when others => null;
 
                        when others => null;
 
                        end case;
 
                        end case;
 
                when "00100000" =>
 
                when "00100000" =>
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                                Inc_PC <= '1';
 
                                Inc_PC <= '1';
 
                                if F(6) = '1' then
 
                                if F(6) = '1' then
 
                                        MCycles <= "010";
 
                                        MCycles <= "010";
 
                                end if;
 
                                end if;
 
                        when 3 =>
 
                        when 3 =>
 
 
 
                                NoRead <= '1';
 
                                JumpE <= '1';
 
                                JumpE <= '1';
 
                                TStates <= "101";
 
                                TStates <= "101";
 
                        when others => null;
 
                        when others => null;
 
                        end case;
 
                        end case;
 
                when "11101001" =>
 
                when "11101001" =>
Line 870... Line 881... 
                                ALU_Op <= "1010";
 
                                ALU_Op <= "1010";
 
                        when 2 =>
 
                        when 2 =>
 
                                I_DJNZ <= '1';
 
                                I_DJNZ <= '1';
 
                                Inc_PC <= '1';
 
                                Inc_PC <= '1';
 
                        when 3 =>
 
                        when 3 =>
 
 
 
                                NoRead <= '1';
 
                                JumpE <= '1';
 
                                JumpE <= '1';
 
                                TStates <= "101";
 
                                TStates <= "101";
 
                        when others => null;
 
                        when others => null;
 
                        end case;
 
                        end case;
 
 
 
 
Line 1316... Line 1328... 
                                        end if;
 
                                        end if;
 
                                        if IR(4) = '1' and F(2) = '1' then
 
                                        if IR(4) = '1' and F(2) = '1' then
 
                                                MCycles <= "100";
 
                                                MCycles <= "100";
 
                                        end if;
 
                                        end if;
 
                                when 4 =>
 
                                when 4 =>
 
 
 
                                        NoRead <= '1';
 
                                        I_BTR <= '1';
 
                                        I_BTR <= '1';
 
                                        TStates <= "101";
 
                                        TStates <= "101";
 
                                        MCycles <= "100";
 
                                        MCycles <= "100";
 
                                when others => null;
 
                                when others => null;
 
                                end case;
 
                                end case;
Line 1340... Line 1353... 
                                                IncDec_16 <= "0110";
 
                                                IncDec_16 <= "0110";
 
                                        else
 
                                        else
 
                                                IncDec_16 <= "1110";
 
                                                IncDec_16 <= "1110";
 
                                        end if;
 
                                        end if;
 
                                when 3 =>
 
                                when 3 =>
 
 
 
                                        NoRead <= '1';
 
                                        I_BC <= '1';
 
                                        I_BC <= '1';
 
                                        TStates <= "101";
 
                                        TStates <= "101";
 
                                        if IR(4) = '1' and F(2) = '1' and F(6) = '0' then
 
                                        if IR(4) = '1' and F(2) = '1' and F(6) = '0' then
 
                                                MCycles <= "100";
 
                                                MCycles <= "100";
 
                                        end if;
 
                                        end if;
 
                                when 4 =>
 
                                when 4 =>
 
 
 
                                        NoRead <= '1';
 
                                        I_BTR <= '1';
 
                                        I_BTR <= '1';
 
                                        TStates <= "101";
 
                                        TStates <= "101";
 
                                        MCycles <= "100";
 
                                        MCycles <= "100";
 
                                when others => null;
 
                                when others => null;
 
                                end case;
 
                                end case;
Line 1373... Line 1388... 
                        when "01001010"|"01011010"|"01101010"|"01111010" =>
 
                        when "01001010"|"01011010"|"01101010"|"01111010" =>
 
                                -- ADC HL,ss
 
                                -- ADC HL,ss
 
                                MCycles <= "011";
 
                                MCycles <= "011";
 
                                case to_integer(unsigned(MCycle)) is
 
                                case to_integer(unsigned(MCycle)) is
 
                                when 2 =>
 
                                when 2 =>
 
 
 
                                        NoRead <= '1';
 
                                        ALU_Op <= "1001";
 
                                        ALU_Op <= "1001";
 
                                        Read_To_Reg <= '1';
 
                                        Read_To_Reg <= '1';
 
                                        Save_ALU <= '1';
 
                                        Save_ALU <= '1';
 
                                        Set_BusA_To(2 downto 0) <= "101";
 
                                        Set_BusA_To(2 downto 0) <= "101";
 
                                        case to_integer(unsigned(IR(5 downto 4))) is
 
                                        case to_integer(unsigned(IR(5 downto 4))) is
Line 1385... Line 1401... 
                                        Set_BusB_To(0) <= '1';
 
                                        Set_BusB_To(0) <= '1';
 
                                                when others =>
 
                                                when others =>
 
                                                Set_BusB_To <= "1000";
 
                                                Set_BusB_To <= "1000";
 
                                        end case;
 
                                        end case;
 
                                when 3 =>
 
                                when 3 =>
 
 
 
                                        NoRead <= '1';
 
                                        Read_To_Reg <= '1';
 
                                        Read_To_Reg <= '1';
 
                                        Save_ALU <= '1';
 
                                        Save_ALU <= '1';
 
                                        ALU_Op <= "1001";
 
                                        ALU_Op <= "1001";
 
                                        Set_BusA_To(2 downto 0) <= "100";
 
                                        Set_BusA_To(2 downto 0) <= "100";
 
                                        case to_integer(unsigned(IR(5 downto 4))) is
 
                                        case to_integer(unsigned(IR(5 downto 4))) is
Line 1404... Line 1421... 
                        when "01000010"|"01010010"|"01100010"|"01110010" =>
 
                        when "01000010"|"01010010"|"01100010"|"01110010" =>
 
                                -- SBC HL,ss
 
                                -- SBC HL,ss
 
                                MCycles <= "011";
 
                                MCycles <= "011";
 
                                case to_integer(unsigned(MCycle)) is
 
                                case to_integer(unsigned(MCycle)) is
 
                                when 2 =>
 
                                when 2 =>
 
 
 
                                        NoRead <= '1';
 
                                        ALU_Op <= "1011";
 
                                        ALU_Op <= "1011";
 
                                        Read_To_Reg <= '1';
 
                                        Read_To_Reg <= '1';
 
                                        Save_ALU <= '1';
 
                                        Save_ALU <= '1';
 
                                        Set_BusA_To(2 downto 0) <= "101";
 
                                        Set_BusA_To(2 downto 0) <= "101";
 
                                        case to_integer(unsigned(IR(5 downto 4))) is
 
                                        case to_integer(unsigned(IR(5 downto 4))) is
Line 1416... Line 1434... 
                                                Set_BusB_To(0) <= '1';
 
                                                Set_BusB_To(0) <= '1';
 
                                        when others =>
 
                                        when others =>
 
                                                Set_BusB_To <= "1000";
 
                                                Set_BusB_To <= "1000";
 
                                        end case;
 
                                        end case;
 
                                when 3 =>
 
                                when 3 =>
 
 
 
                                        NoRead <= '1';
 
                                        ALU_Op <= "1011";
 
                                        ALU_Op <= "1011";
 
                                        Read_To_Reg <= '1';
 
                                        Read_To_Reg <= '1';
 
                                        Save_ALU <= '1';
 
                                        Save_ALU <= '1';
 
                                        Set_BusA_To(2 downto 0) <= "100";
 
                                        Set_BusA_To(2 downto 0) <= "100";
 
                                        case to_integer(unsigned(IR(5 downto 4))) is
 
                                        case to_integer(unsigned(IR(5 downto 4))) is
Line 1434... Line 1453... 
                        when "01101111" =>
 
                        when "01101111" =>
 
                                -- RLD
 
                                -- RLD
 
                                MCycles <= "100";
 
                                MCycles <= "100";
 
                                case to_integer(unsigned(MCycle)) is
 
                                case to_integer(unsigned(MCycle)) is
 
                                when 2 =>
 
                                when 2 =>
 
 
 
                                        NoRead <= '1';
 
                                        Set_Addr_To <= aXY;
 
                                        Set_Addr_To <= aXY;
 
                                when 3 =>
 
                                when 3 =>
 
                                        Read_To_Reg <= '1';
 
                                        Read_To_Reg <= '1';
 
                                        Set_BusB_To(2 downto 0) <= "110";
 
                                        Set_BusB_To(2 downto 0) <= "110";
 
                                        Set_BusA_To(2 downto 0) <= "111";
 
                                        Set_BusA_To(2 downto 0) <= "111";
Line 1542... Line 1562... 
                                        Write <= '1';
 
                                        Write <= '1';
 
                                        if IR(4) = '1' and F(6) = '0' then
 
                                        if IR(4) = '1' and F(6) = '0' then
 
                                                MCycles <= "100";
 
                                                MCycles <= "100";
 
                                        end if;
 
                                        end if;
 
                                when 4 =>
 
                                when 4 =>
 
 
 
                                        NoRead <= '1';
 
                                        I_BTR <= '1';
 
                                        I_BTR <= '1';
 
                                        TStates <= "101";
 
                                        TStates <= "101";
 
                                        MCycles <= "100";
 
                                        MCycles <= "100";
 
                                when others => null;
 
                                when others => null;
 
                                end case;
 
                                end case;
Line 1575... Line 1596... 
                                        Write <= '1';
 
                                        Write <= '1';
 
                                        if IR(4) = '1' and F(6) = '0' then
 
                                        if IR(4) = '1' and F(6) = '0' then
 
                                                MCycles <= "100";
 
                                                MCycles <= "100";
 
                                        end if;
 
                                        end if;
 
                                when 4 =>
 
                                when 4 =>
 
 
 
                                        NoRead <= '1';
 
                                        I_BTR <= '1';
 
                                        I_BTR <= '1';
 
                                        TStates <= "101";
 
                                        TStates <= "101";
 
                                        MCycles <= "100";
 
                                        MCycles <= "100";
 
                                when others => null;
 
                                when others => null;
 
                                end case;
 
                                end case;

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