| Line 1... |
Line 1... |
--
|
--
|
-- Z80 compatible microprocessor core
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-- Z80 compatible microprocessor core
|
--
|
--
|
-- Version : 0240
|
-- Version : 0242
|
--
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 56... |
Line 56... |
--
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--
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-- 0238b: Fixed instruction timing for POP and DJNZ
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-- 0238b: Fixed instruction timing for POP and DJNZ
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--
|
--
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-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
|
-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
|
--
|
--
|
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-- 0242 : Fixed I/O instruction timing, cleanup
|
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--
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|
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.T80_Pack.all;
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|
|
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entity T80_MCode is
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entity T80_MCode is
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generic(
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generic(
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Mode : integer := 0;
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Mode : integer := 0;
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Flag_C : integer := 0;
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Flag_C : integer := 0;
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| Line 92... |
Line 93... |
Read_To_Reg : out std_logic;
|
Read_To_Reg : out std_logic;
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Read_To_Acc : out std_logic;
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Read_To_Acc : out std_logic;
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Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
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Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
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Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
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Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
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ALU_Op : out std_logic_vector(3 downto 0);
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ALU_Op : out std_logic_vector(3 downto 0);
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-- (ir)ADD, (ir)ADC, (ir)SUB, (ir)SBC, (ir)AND, (ir)XOR, (ir)OR, (ir)CP, ADD, ADC, SUB, SBC, DAA, RLD, RRD, CP
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-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
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Rot_Op : out std_logic;
|
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Bit_Op : out std_logic_vector(1 downto 0); -- None, BIT, SET, RES
|
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Save_ALU : out std_logic;
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Save_ALU : out std_logic;
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PreserveC : out std_logic;
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PreserveC : out std_logic;
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Arith16 : out std_logic;
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Arith16 : out std_logic;
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Set_Addr_To : out AddressOutput; -- aXY,aIOA,aSP,aBC,aDE,aZI,aNone
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Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
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IORQ : out std_logic;
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IORQ : out std_logic;
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Jump : out std_logic;
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Jump : out std_logic;
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JumpE : out std_logic;
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JumpE : out std_logic;
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JumpXY : out std_logic;
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JumpXY : out std_logic;
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Call : out std_logic;
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Call : out std_logic;
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| Line 135... |
Line 134... |
);
|
);
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end T80_MCode;
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end T80_MCode;
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|
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architecture rtl of T80_MCode is
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architecture rtl of T80_MCode is
|
|
|
|
constant aNone : std_logic_vector(2 downto 0) := "111";
|
|
constant aBC : std_logic_vector(2 downto 0) := "000";
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constant aDE : std_logic_vector(2 downto 0) := "001";
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constant aXY : std_logic_vector(2 downto 0) := "010";
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constant aIOA : std_logic_vector(2 downto 0) := "100";
|
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constant aSP : std_logic_vector(2 downto 0) := "101";
|
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constant aZI : std_logic_vector(2 downto 0) := "110";
|
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-- constant aNone : std_logic_vector(2 downto 0) := "000";
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-- constant aXY : std_logic_vector(2 downto 0) := "001";
|
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-- constant aIOA : std_logic_vector(2 downto 0) := "010";
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-- constant aSP : std_logic_vector(2 downto 0) := "011";
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-- constant aBC : std_logic_vector(2 downto 0) := "100";
|
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-- constant aDE : std_logic_vector(2 downto 0) := "101";
|
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-- constant aZI : std_logic_vector(2 downto 0) := "110";
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|
|
function is_cc_true(
|
function is_cc_true(
|
F : std_logic_vector(7 downto 0);
|
F : std_logic_vector(7 downto 0);
|
cc : bit_vector(2 downto 0)
|
cc : bit_vector(2 downto 0)
|
) return boolean is
|
) return boolean is
|
begin
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begin
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| Line 192... |
Line 206... |
IncDec_16 <= "0000";
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IncDec_16 <= "0000";
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Read_To_Acc <= '0';
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Read_To_Acc <= '0';
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Read_To_Reg <= '0';
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Read_To_Reg <= '0';
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Set_BusB_To <= "0000";
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Set_BusB_To <= "0000";
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Set_BusA_To <= "0000";
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Set_BusA_To <= "0000";
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ALU_Op <= "0000";
|
ALU_Op <= "0" & IR(5 downto 3);
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Rot_Op <= '0';
|
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Bit_Op <= "00";
|
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Save_ALU <= '0';
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Save_ALU <= '0';
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PreserveC <= '0';
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PreserveC <= '0';
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Arith16 <= '0';
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Arith16 <= '0';
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IORQ <= '0';
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IORQ <= '0';
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Set_Addr_To <= aNone;
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Set_Addr_To <= aNone;
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| Line 704... |
Line 716... |
Set_BusB_To <= "1010";
|
Set_BusB_To <= "1010";
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Set_BusA_To(2 downto 0) <= DDD;
|
Set_BusA_To(2 downto 0) <= DDD;
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Read_To_Reg <= '1';
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Read_To_Reg <= '1';
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Save_ALU <= '1';
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Save_ALU <= '1';
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PreserveC <= '1';
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PreserveC <= '1';
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ALU_Op <= "1000";
|
ALU_Op <= "0000";
|
when "00110100" =>
|
when "00110100" =>
|
-- INC (HL)
|
-- INC (HL)
|
MCycles <= "011";
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MCycles <= "011";
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case to_integer(unsigned(MCycle)) is
|
case to_integer(unsigned(MCycle)) is
|
when 1 =>
|
when 1 =>
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| Line 717... |
Line 729... |
TStates <= "100";
|
TStates <= "100";
|
Set_Addr_To <= aXY;
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Set_Addr_To <= aXY;
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Read_To_Reg <= '1';
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Read_To_Reg <= '1';
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Save_ALU <= '1';
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Save_ALU <= '1';
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PreserveC <= '1';
|
PreserveC <= '1';
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ALU_Op <= "1000";
|
ALU_Op <= "0000";
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Set_BusB_To <= "1010";
|
Set_BusB_To <= "1010";
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Set_BusA_To(2 downto 0) <= DDD;
|
Set_BusA_To(2 downto 0) <= DDD;
|
when 3 =>
|
when 3 =>
|
Write <= '1';
|
Write <= '1';
|
when others => null;
|
when others => null;
|
| Line 731... |
Line 743... |
Set_BusB_To <= "1010";
|
Set_BusB_To <= "1010";
|
Set_BusA_To(2 downto 0) <= DDD;
|
Set_BusA_To(2 downto 0) <= DDD;
|
Read_To_Reg <= '1';
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Read_To_Reg <= '1';
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Save_ALU <= '1';
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Save_ALU <= '1';
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PreserveC <= '1';
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PreserveC <= '1';
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ALU_Op <= "1010";
|
ALU_Op <= "0010";
|
when "00110101" =>
|
when "00110101" =>
|
-- DEC (HL)
|
-- DEC (HL)
|
MCycles <= "011";
|
MCycles <= "011";
|
case to_integer(unsigned(MCycle)) is
|
case to_integer(unsigned(MCycle)) is
|
when 1 =>
|
when 1 =>
|
Set_Addr_To <= aXY;
|
Set_Addr_To <= aXY;
|
when 2 =>
|
when 2 =>
|
TStates <= "100";
|
TStates <= "100";
|
Set_Addr_To <= aXY;
|
Set_Addr_To <= aXY;
|
ALU_Op <= "1010";
|
ALU_Op <= "0010";
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
PreserveC <= '1';
|
PreserveC <= '1';
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Set_BusB_To <= "1010";
|
Set_BusB_To <= "1010";
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Set_BusA_To(2 downto 0) <= DDD;
|
Set_BusA_To(2 downto 0) <= DDD;
|
| Line 835... |
Line 847... |
-- ADD HL,ss
|
-- ADD HL,ss
|
MCycles <= "011";
|
MCycles <= "011";
|
case to_integer(unsigned(MCycle)) is
|
case to_integer(unsigned(MCycle)) is
|
when 2 =>
|
when 2 =>
|
NoRead <= '1';
|
NoRead <= '1';
|
ALU_Op <= "1000";
|
ALU_Op <= "0000";
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Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
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Save_ALU <= '1';
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Set_BusA_To(2 downto 0) <= "101";
|
Set_BusA_To(2 downto 0) <= "101";
|
case to_integer(unsigned(IR(5 downto 4))) is
|
case to_integer(unsigned(IR(5 downto 4))) is
|
when 0|1|2 =>
|
when 0|1|2 =>
|
| Line 852... |
Line 864... |
Arith16 <= '1';
|
Arith16 <= '1';
|
when 3 =>
|
when 3 =>
|
NoRead <= '1';
|
NoRead <= '1';
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
ALU_Op <= "1001";
|
ALU_Op <= "0001";
|
Set_BusA_To(2 downto 0) <= "100";
|
Set_BusA_To(2 downto 0) <= "100";
|
case to_integer(unsigned(IR(5 downto 4))) is
|
case to_integer(unsigned(IR(5 downto 4))) is
|
when 0|1|2 =>
|
when 0|1|2 =>
|
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
|
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
|
when others =>
|
when others =>
|
| Line 884... |
Line 896... |
|"00001111"
|
|"00001111"
|
-- RRCA
|
-- RRCA
|
|"00011111" =>
|
|"00011111" =>
|
-- RRA
|
-- RRA
|
Set_BusA_To(2 downto 0) <= "111";
|
Set_BusA_To(2 downto 0) <= "111";
|
Rot_Op <= '1';
|
ALU_Op <= "1000";
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
|
|
-- JUMP GROUP
|
-- JUMP GROUP
|
when "11000011" =>
|
when "11000011" =>
|
| Line 1071... |
Line 1083... |
I_DJNZ <= '1';
|
I_DJNZ <= '1';
|
Set_BusB_To <= "1010";
|
Set_BusB_To <= "1010";
|
Set_BusA_To(2 downto 0) <= "000";
|
Set_BusA_To(2 downto 0) <= "000";
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
ALU_Op <= "1010";
|
ALU_Op <= "0010";
|
when 2 =>
|
when 2 =>
|
I_DJNZ <= '1';
|
I_DJNZ <= '1';
|
Inc_PC <= '1';
|
Inc_PC <= '1';
|
when 3 =>
|
when 3 =>
|
NoRead <= '1';
|
NoRead <= '1';
|
| Line 1174... |
Line 1186... |
when "01" =>
|
when "01" =>
|
-- ADD SP,n
|
-- ADD SP,n
|
MCycles <= "011";
|
MCycles <= "011";
|
case to_integer(unsigned(MCycle)) is
|
case to_integer(unsigned(MCycle)) is
|
when 2 =>
|
when 2 =>
|
ALU_Op <= "1000";
|
ALU_Op <= "0000";
|
Inc_PC <= '1';
|
Inc_PC <= '1';
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
Set_BusA_To <= "1000";
|
Set_BusA_To <= "1000";
|
Set_BusB_To <= "0110";
|
Set_BusB_To <= "0110";
|
when 3 =>
|
when 3 =>
|
NoRead <= '1';
|
NoRead <= '1';
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
ALU_Op <= "1001";
|
ALU_Op <= "0001";
|
Set_BusA_To <= "1001";
|
Set_BusA_To <= "1001";
|
Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
|
Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
|
when others =>
|
when others =>
|
end case;
|
end case;
|
when "10" =>
|
when "10" =>
|
| Line 1345... |
Line 1357... |
-- RR r
|
-- RR r
|
-- SLA r
|
-- SLA r
|
-- SRA r
|
-- SRA r
|
-- SRL r
|
-- SRL r
|
-- SLL r (Undocumented) / SWAP r
|
-- SLL r (Undocumented) / SWAP r
|
Rot_Op <= '1';
|
if MCycle = "001" then
|
|
ALU_Op <= "1000";
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
|
end if;
|
when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
|
when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
|
-- RLC (HL)
|
-- RLC (HL)
|
-- RL (HL)
|
-- RL (HL)
|
-- RRC (HL)
|
-- RRC (HL)
|
-- RR (HL)
|
-- RR (HL)
|
| Line 1359... |
Line 1373... |
-- SRL (HL)
|
-- SRL (HL)
|
-- SLA (HL)
|
-- SLA (HL)
|
-- SLL (HL) (Undocumented) / SWAP (HL)
|
-- SLL (HL) (Undocumented) / SWAP (HL)
|
MCycles <= "011";
|
MCycles <= "011";
|
case to_integer(unsigned(MCycle)) is
|
case to_integer(unsigned(MCycle)) is
|
when 1 =>
|
when 1 | 7 =>
|
Set_Addr_To <= aXY;
|
Set_Addr_To <= aXY;
|
when 2 =>
|
when 2 =>
|
Rot_Op <= '1';
|
ALU_Op <= "1000";
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
Set_Addr_To <= aXY;
|
Set_Addr_To <= aXY;
|
TStates <= "100";
|
TStates <= "100";
|
when 3 =>
|
when 3 =>
|
| Line 1380... |
Line 1394... |
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|
|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
|
|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
|
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
|
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
|
-- BIT b,r
|
-- BIT b,r
|
|
if MCycle = "001" then
|
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
|
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
|
Bit_Op <= "01";
|
ALU_Op <= "1001";
|
|
end if;
|
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
|
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
|
-- BIT b,(HL)
|
-- BIT b,(HL)
|
MCycles <= "010";
|
MCycles <= "010";
|
case to_integer(unsigned(MCycle)) is
|
case to_integer(unsigned(MCycle)) is
|
when 1 =>
|
when 1 | 7 =>
|
Set_Addr_To <= aXY;
|
Set_Addr_To <= aXY;
|
when 2 =>
|
when 2 =>
|
Bit_Op <= "01";
|
ALU_Op <= "1001";
|
TStates <= "100";
|
TStates <= "100";
|
when others => null;
|
when others =>
|
end case;
|
end case;
|
when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
|
when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
|
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
|
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
|
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
|
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
|
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
|
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
|
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
|
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
|
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
|
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
|
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
|
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
|
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
|
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
|
-- SET b,r
|
-- SET b,r
|
Bit_Op <= "10";
|
if MCycle = "001" then
|
|
ALU_Op <= "1010";
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
|
end if;
|
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
|
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
|
-- SET b,(HL)
|
-- SET b,(HL)
|
MCycles <= "011";
|
MCycles <= "011";
|
case to_integer(unsigned(MCycle)) is
|
case to_integer(unsigned(MCycle)) is
|
when 1 =>
|
when 1 | 7 =>
|
Set_Addr_To <= aXY;
|
Set_Addr_To <= aXY;
|
when 2 =>
|
when 2 =>
|
Bit_Op <= "10";
|
ALU_Op <= "1010";
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
Set_Addr_To <= aXY;
|
Set_Addr_To <= aXY;
|
TStates <= "100";
|
TStates <= "100";
|
when 3 =>
|
when 3 =>
|
Write <= '1';
|
Write <= '1';
|
when others => null;
|
when others =>
|
end case;
|
end case;
|
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
|
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
|
-- RES b,r
|
-- RES b,r
|
Bit_Op <= "11";
|
if MCycle = "001" then
|
|
ALU_Op <= "1011";
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
|
end if;
|
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
|
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
|
-- RES b,(HL)
|
-- RES b,(HL)
|
MCycles <= "011";
|
MCycles <= "011";
|
case to_integer(unsigned(MCycle)) is
|
case to_integer(unsigned(MCycle)) is
|
when 1 =>
|
when 1 | 7 =>
|
Set_Addr_To <= aXY;
|
Set_Addr_To <= aXY;
|
when 2 =>
|
when 2 =>
|
Bit_Op <= "11";
|
ALU_Op <= "1011";
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
Set_Addr_To <= aXY;
|
Set_Addr_To <= aXY;
|
TStates <= "100";
|
TStates <= "100";
|
when 3 =>
|
when 3 =>
|
Write <= '1';
|
Write <= '1';
|
when others => null;
|
when others =>
|
end case;
|
end case;
|
end case;
|
end case;
|
|
|
when others =>
|
when others =>
|
|
|
| Line 1574... |
Line 1594... |
Write <= '1';
|
Write <= '1';
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
when "10100000" | "10101000" | "10110000" | "10111000" =>
|
when "10100000" | "10101000" | "10110000" | "10111000" =>
|
-- LDI, LDD, LDIR, LDDR
|
-- LDI, LDD, LDIR, LDDR
|
MCycles <= "011";
|
MCycles <= "100";
|
case to_integer(unsigned(MCycle)) is
|
case to_integer(unsigned(MCycle)) is
|
when 1 =>
|
when 1 =>
|
Set_Addr_To <= aXY;
|
Set_Addr_To <= aXY;
|
IncDec_16 <= "1100"; -- BC
|
IncDec_16 <= "1100"; -- BC
|
when 2 =>
|
when 2 =>
|
Set_BusB_To <= "0110";
|
Set_BusB_To <= "0110";
|
Set_BusA_To(2 downto 0) <= "111";
|
Set_BusA_To(2 downto 0) <= "111";
|
ALU_Op <= "1000";
|
ALU_Op <= "0000";
|
Set_Addr_To <= aDE;
|
Set_Addr_To <= aDE;
|
if IR(3) = '0' then
|
if IR(3) = '0' then
|
IncDec_16 <= "0110"; -- IX
|
IncDec_16 <= "0110"; -- IX
|
else
|
else
|
IncDec_16 <= "1110";
|
IncDec_16 <= "1110";
|
| Line 1598... |
Line 1618... |
if IR(3) = '0' then
|
if IR(3) = '0' then
|
IncDec_16 <= "0101"; -- DE
|
IncDec_16 <= "0101"; -- DE
|
else
|
else
|
IncDec_16 <= "1101";
|
IncDec_16 <= "1101";
|
end if;
|
end if;
|
if IR(4) = '1' and F(Flag_P) = '1' then
|
|
MCycles <= "100";
|
|
end if;
|
|
when 4 =>
|
when 4 =>
|
NoRead <= '1';
|
NoRead <= '1';
|
I_BTR <= '1';
|
|
TStates <= "101";
|
TStates <= "101";
|
MCycles <= "100";
|
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
when "10100001" | "10101001" | "10110001" | "10111001" =>
|
when "10100001" | "10101001" | "10110001" | "10111001" =>
|
-- CPI, CPD, CPIR, CPDR
|
-- CPI, CPD, CPIR, CPDR
|
MCycles <= "011";
|
MCycles <= "100";
|
case to_integer(unsigned(MCycle)) is
|
case to_integer(unsigned(MCycle)) is
|
when 1 =>
|
when 1 =>
|
Set_Addr_To <= aXY;
|
Set_Addr_To <= aXY;
|
IncDec_16 <= "1100"; -- BC
|
IncDec_16 <= "1100"; -- BC
|
when 2 =>
|
when 2 =>
|
Set_BusB_To <= "0110";
|
Set_BusB_To <= "0110";
|
Set_BusA_To(2 downto 0) <= "111";
|
Set_BusA_To(2 downto 0) <= "111";
|
ALU_Op <= "1111";
|
ALU_Op <= "0111";
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
PreserveC <= '1';
|
PreserveC <= '1';
|
if IR(3) = '0' then
|
if IR(3) = '0' then
|
IncDec_16 <= "0110";
|
IncDec_16 <= "0110";
|
else
|
else
|
| Line 1630... |
Line 1645... |
end if;
|
end if;
|
when 3 =>
|
when 3 =>
|
NoRead <= '1';
|
NoRead <= '1';
|
I_BC <= '1';
|
I_BC <= '1';
|
TStates <= "101";
|
TStates <= "101";
|
if IR(4) = '1' and F(Flag_P) = '1' and F(Flag_Z) = '0' then
|
|
MCycles <= "100";
|
|
end if;
|
|
when 4 =>
|
when 4 =>
|
NoRead <= '1';
|
NoRead <= '1';
|
I_BTR <= '1';
|
|
TStates <= "101";
|
TStates <= "101";
|
MCycles <= "100";
|
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
|
when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
|
-- NEG
|
-- NEG
|
Alu_OP <= "1010";
|
Alu_OP <= "0010";
|
Set_BusB_To <= "0111";
|
Set_BusB_To <= "0111";
|
Set_BusA_To <= "1010";
|
Set_BusA_To <= "1010";
|
Read_To_Acc <= '1';
|
Read_To_Acc <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
when "01000110"|"01001110"|"01100110"|"01101110" =>
|
when "01000110"|"01001110"|"01100110"|"01101110" =>
|
| Line 1663... |
Line 1673... |
-- ADC HL,ss
|
-- ADC HL,ss
|
MCycles <= "011";
|
MCycles <= "011";
|
case to_integer(unsigned(MCycle)) is
|
case to_integer(unsigned(MCycle)) is
|
when 2 =>
|
when 2 =>
|
NoRead <= '1';
|
NoRead <= '1';
|
ALU_Op <= "1001";
|
ALU_Op <= "0001";
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
Set_BusA_To(2 downto 0) <= "101";
|
Set_BusA_To(2 downto 0) <= "101";
|
case to_integer(unsigned(IR(5 downto 4))) is
|
case to_integer(unsigned(IR(5 downto 4))) is
|
when 0|1|2 =>
|
when 0|1|2 =>
|
| Line 1679... |
Line 1689... |
TStates <= "100";
|
TStates <= "100";
|
when 3 =>
|
when 3 =>
|
NoRead <= '1';
|
NoRead <= '1';
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
ALU_Op <= "1001";
|
ALU_Op <= "0001";
|
Set_BusA_To(2 downto 0) <= "100";
|
Set_BusA_To(2 downto 0) <= "100";
|
case to_integer(unsigned(IR(5 downto 4))) is
|
case to_integer(unsigned(IR(5 downto 4))) is
|
when 0|1|2 =>
|
when 0|1|2 =>
|
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
|
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
|
Set_BusB_To(0) <= '0';
|
Set_BusB_To(0) <= '0';
|
| Line 1696... |
Line 1706... |
-- SBC HL,ss
|
-- SBC HL,ss
|
MCycles <= "011";
|
MCycles <= "011";
|
case to_integer(unsigned(MCycle)) is
|
case to_integer(unsigned(MCycle)) is
|
when 2 =>
|
when 2 =>
|
NoRead <= '1';
|
NoRead <= '1';
|
ALU_Op <= "1011";
|
ALU_Op <= "0011";
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
Set_BusA_To(2 downto 0) <= "101";
|
Set_BusA_To(2 downto 0) <= "101";
|
case to_integer(unsigned(IR(5 downto 4))) is
|
case to_integer(unsigned(IR(5 downto 4))) is
|
when 0|1|2 =>
|
when 0|1|2 =>
|
| Line 1710... |
Line 1720... |
Set_BusB_To <= "1000";
|
Set_BusB_To <= "1000";
|
end case;
|
end case;
|
TStates <= "100";
|
TStates <= "100";
|
when 3 =>
|
when 3 =>
|
NoRead <= '1';
|
NoRead <= '1';
|
ALU_Op <= "1011";
|
ALU_Op <= "0011";
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
Set_BusA_To(2 downto 0) <= "100";
|
Set_BusA_To(2 downto 0) <= "100";
|
case to_integer(unsigned(IR(5 downto 4))) is
|
case to_integer(unsigned(IR(5 downto 4))) is
|
when 0|1|2 =>
|
when 0|1|2 =>
|
| Line 1810... |
Line 1820... |
IORQ <= '1';
|
IORQ <= '1';
|
when others =>
|
when others =>
|
end case;
|
end case;
|
when "10100010" | "10101010" | "10110010" | "10111010" =>
|
when "10100010" | "10101010" | "10110010" | "10111010" =>
|
-- INI, IND, INIR, INDR
|
-- INI, IND, INIR, INDR
|
MCycles <= "011";
|
MCycles <= "100";
|
case to_integer(unsigned(MCycle)) is
|
case to_integer(unsigned(MCycle)) is
|
when 1 =>
|
when 1 =>
|
TStates <= "101";
|
|
Set_Addr_To <= aBC;
|
Set_Addr_To <= aBC;
|
Set_BusB_To <= "1010";
|
Set_BusB_To <= "1010";
|
Set_BusA_To <= "0000";
|
Set_BusA_To <= "0000";
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
ALU_Op <= "1010";
|
ALU_Op <= "0010";
|
when 2 =>
|
when 2 =>
|
IORQ <= '1';
|
IORQ <= '1';
|
Set_BusB_To <= "0110";
|
Set_BusB_To <= "0110";
|
Set_Addr_To <= aXY;
|
Set_Addr_To <= aXY;
|
when 3 =>
|
when 3 =>
|
| Line 1832... |
Line 1841... |
else
|
else
|
IncDec_16 <= "1010";
|
IncDec_16 <= "1010";
|
end if;
|
end if;
|
TStates <= "100";
|
TStates <= "100";
|
Write <= '1';
|
Write <= '1';
|
if IR(4) = '1' and F(Flag_Z) = '0' then
|
I_BTR <= '1';
|
MCycles <= "100";
|
|
end if;
|
|
when 4 =>
|
when 4 =>
|
NoRead <= '1';
|
NoRead <= '1';
|
I_BTR <= '1';
|
|
TStates <= "101";
|
TStates <= "101";
|
MCycles <= "100";
|
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
when "10100011" | "10101011" | "10110011" | "10111011" =>
|
when "10100011" | "10101011" | "10110011" | "10111011" =>
|
-- OUTI, OUTD, OTIR, OTDR
|
-- OUTI, OUTD, OTIR, OTDR
|
MCycles <= "011";
|
MCycles <= "100";
|
case to_integer(unsigned(MCycle)) is
|
case to_integer(unsigned(MCycle)) is
|
when 1 =>
|
when 1 =>
|
TStates <= "101";
|
TStates <= "101";
|
Set_Addr_To <= aXY;
|
Set_Addr_To <= aXY;
|
Set_BusB_To <= "1010";
|
Set_BusB_To <= "1010";
|
Set_BusA_To <= "0000";
|
Set_BusA_To <= "0000";
|
Read_To_Reg <= '1';
|
Read_To_Reg <= '1';
|
Save_ALU <= '1';
|
Save_ALU <= '1';
|
ALU_Op <= "1010";
|
ALU_Op <= "0010";
|
when 2 =>
|
when 2 =>
|
Set_BusB_To <= "0110";
|
Set_BusB_To <= "0110";
|
Set_Addr_To <= aBC;
|
Set_Addr_To <= aBC;
|
when 3 =>
|
when 3 =>
|
if IR(3) = '0' then
|
if IR(3) = '0' then
|
IncDec_16 <= "0010";
|
IncDec_16 <= "0010";
|
else
|
else
|
IncDec_16 <= "1010";
|
IncDec_16 <= "1010";
|
end if;
|
end if;
|
IORQ <= '1';
|
IORQ <= '1';
|
TStates <= "100";
|
|
Write <= '1';
|
Write <= '1';
|
if IR(4) = '1' and F(Flag_Z) = '0' then
|
I_BTR <= '1';
|
MCycles <= "100";
|
|
end if;
|
|
when 4 =>
|
when 4 =>
|
NoRead <= '1';
|
NoRead <= '1';
|
I_BTR <= '1';
|
|
TStates <= "101";
|
TStates <= "101";
|
MCycles <= "100";
|
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end case;
|
end case;
|
|
|
end case;
|
end case;
|
| Line 1899... |
Line 1899... |
end if;
|
end if;
|
|
|
if Mode < 2 then
|
if Mode < 2 then
|
if MCycle = "110" then
|
if MCycle = "110" then
|
Inc_PC <= '1';
|
Inc_PC <= '1';
|
Set_Addr_To <= aNone;
|
|
if Mode = 1 then
|
if Mode = 1 then
|
TStates <= "100";
|
|
Set_Addr_To <= aXY;
|
Set_Addr_To <= aXY;
|
|
TStates <= "100";
|
Set_BusB_To(2 downto 0) <= SSS;
|
Set_BusB_To(2 downto 0) <= SSS;
|
Set_BusB_To(3) <= '0';
|
Set_BusB_To(3) <= '0';
|
|
end if;
|
if IRB = "00110110" or IRB = "11001011" then
|
if IRB = "00110110" or IRB = "11001011" then
|
Set_Addr_To <= aNone;
|
Set_Addr_To <= aNone;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
if MCycle = "111" then
|
if MCycle = "111" then
|
|
if Mode = 0 then
|
TStates <= "101";
|
TStates <= "101";
|
|
end if;
|
|
if ISet /= "01" then
|
Set_Addr_To <= aXY;
|
Set_Addr_To <= aXY;
|
|
end if;
|
Set_BusB_To(2 downto 0) <= SSS;
|
Set_BusB_To(2 downto 0) <= SSS;
|
Set_BusB_To(3) <= '0';
|
Set_BusB_To(3) <= '0';
|
if IRB = "00110110" then
|
if IRB = "00110110" or ISet = "01" then
|
-- LD (HL),n
|
-- LD (HL),n
|
Inc_PC <= '1';
|
Inc_PC <= '1';
|
else
|
else
|
NoRead <= '1';
|
NoRead <= '1';
|
end if;
|
end if;
|
