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https://opencores.org/ocsvn/t80/t80/trunk
[/] [t80/] [trunk/] [rtl/] [vhdl/] [T80_Pack.vhd] - Diff between revs 22 and 25
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| Rev 22 |
Rev 25 |
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--
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--
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-- Z80 compatible microprocessor core
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-- Z80 compatible microprocessor core
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--
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--
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-- Version : 0237
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-- Version : 0238
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--
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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INT_n : in std_logic;
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INT_n : in std_logic;
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NMI_n : in std_logic;
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NMI_n : in std_logic;
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BUSRQ_n : in std_logic;
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BUSRQ_n : in std_logic;
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M1_n : out std_logic;
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M1_n : out std_logic;
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IORQ : out std_logic;
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IORQ : out std_logic;
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NoRead : out std_logic;
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Write : out std_logic;
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Write : out std_logic;
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RFSH_n : out std_logic;
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RFSH_n : out std_logic;
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HALT_n : out std_logic;
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HALT_n : out std_logic;
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BUSAK_n : out std_logic;
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BUSAK_n : out std_logic;
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A : out std_logic_vector(15 downto 0);
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A : out std_logic_vector(15 downto 0);
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I_INRC : out std_logic;
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I_INRC : out std_logic;
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SetDI : out std_logic;
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SetDI : out std_logic;
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SetEI : out std_logic;
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SetEI : out std_logic;
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IMode : out std_logic_vector(1 downto 0);
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IMode : out std_logic_vector(1 downto 0);
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Halt : out std_logic;
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Halt : out std_logic;
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NoRead : out std_logic;
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Write : out std_logic
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Write : out std_logic
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);
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);
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end component;
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end component;
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component T80_ALU
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component T80_ALU
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port(
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port(
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Arith16 : in std_logic;
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Arith16 : in std_logic;
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Z16 : in std_logic;
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ALU_Op : in std_logic_vector(3 downto 0);
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ALU_Op : in std_logic_vector(3 downto 0);
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Rot_Op : in std_logic;
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Rot_Op : in std_logic;
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Bit_Op : in std_logic_vector(1 downto 0);
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Bit_Op : in std_logic_vector(1 downto 0);
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IR : in std_logic_vector(7 downto 0);
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IR : in std_logic_vector(7 downto 0);
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ISet : in std_logic_vector(1 downto 0);
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ISet : in std_logic_vector(1 downto 0);
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