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--
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--
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-- Z80 compatible microprocessor core
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-- Z80 compatible microprocessor core
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--
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--
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-- Version : 0238
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-- Version : 0240
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--
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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package T80_Pack is
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package T80_Pack is
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component T80
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component T80
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generic(
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generic(
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Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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Flag_C : integer := 0;
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Flag_N : integer := 1;
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Flag_P : integer := 2;
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Flag_X : integer := 3;
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Flag_H : integer := 4;
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Flag_Y : integer := 5;
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Flag_Z : integer := 6;
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Flag_S : integer := 7
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);
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);
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port(
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port(
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RESET_n : in std_logic;
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RESET_n : in std_logic;
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CLK_n : in std_logic;
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CLK_n : in std_logic;
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CEN : in std_logic;
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CEN : in std_logic;
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DInst : in std_logic_vector(7 downto 0);
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DInst : in std_logic_vector(7 downto 0);
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DI : in std_logic_vector(7 downto 0);
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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MC : out std_logic_vector(2 downto 0);
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MC : out std_logic_vector(2 downto 0);
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TS : out std_logic_vector(2 downto 0);
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TS : out std_logic_vector(2 downto 0);
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False_M1 : out std_logic;
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IntCycle_n : out std_logic;
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IntCycle_n : out std_logic;
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IntE : out std_logic
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IntE : out std_logic;
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Stop : out std_logic
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);
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);
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end component;
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end component;
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type AddressOutput is (aXY,aIOA,aSP,aBC,aDE,aZI,aNone);
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type AddressOutput is (aXY,aIOA,aSP,aBC,aDE,aZI,aNone);
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component T80_MCode
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component T80_MCode
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generic(
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generic(
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Mode : integer := 0
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Mode : integer := 0;
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Flag_C : integer := 0;
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Flag_N : integer := 1;
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Flag_P : integer := 2;
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Flag_X : integer := 3;
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Flag_H : integer := 4;
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Flag_Y : integer := 5;
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Flag_Z : integer := 6;
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Flag_S : integer := 7
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);
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);
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port(
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port(
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IR : in std_logic_vector(7 downto 0);
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IR : in std_logic_vector(7 downto 0);
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ISet : in std_logic_vector(1 downto 0);
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ISet : in std_logic_vector(1 downto 0);
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MCycle : in std_logic_vector(2 downto 0);
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MCycle : in std_logic_vector(2 downto 0);
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Write : out std_logic
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Write : out std_logic
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);
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);
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end component;
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end component;
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component T80_ALU
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component T80_ALU
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generic(
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Mode : integer := 0;
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Flag_C : integer := 0;
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Flag_N : integer := 1;
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Flag_P : integer := 2;
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Flag_X : integer := 3;
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Flag_H : integer := 4;
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Flag_Y : integer := 5;
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Flag_Z : integer := 6;
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Flag_S : integer := 7
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);
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port(
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port(
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Arith16 : in std_logic;
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Arith16 : in std_logic;
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Z16 : in std_logic;
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Z16 : in std_logic;
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ALU_Op : in std_logic_vector(3 downto 0);
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ALU_Op : in std_logic_vector(3 downto 0);
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Rot_Op : in std_logic;
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Rot_Op : in std_logic;
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