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Line 1... |
--
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--
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-- Z80 compatible microprocessor core, asynchronous top level
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-- Z80 compatible microprocessor core, asynchronous top level
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--
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--
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-- Version : 0211
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-- Version : 0235
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--
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (dwallner@hem2.passagen.se)
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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| Line 36... |
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-- Please report bugs to the author, but before you do so, please
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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-- you have the latest version of this file.
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--
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--
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-- The latest version of this file can be found at:
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-- The latest version of this file can be found at:
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-- http://hem.passagen.se/dwallner/vhdl.html
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-- http://www.opencores.org/cvsweb.shtml/t80/
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--
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--
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-- Limitations :
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-- Limitations :
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--
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--
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-- File history :
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-- File history :
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--
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--
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-- 0208 : First complete release
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-- 0208 : First complete release
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--
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--
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-- 0211 : Fixed interrupt cycle
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-- 0211 : Fixed interrupt cycle
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--
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--
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-- 0235 : Updated for T80 interface change
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.T80_Pack.all;
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use work.T80_Pack.all;
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);
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);
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end T80a;
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end T80a;
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architecture rtl of T80a is
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architecture rtl of T80a is
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|
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signal CEN : std_logic;
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signal Reset_s : std_logic;
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signal Reset_s : std_logic;
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signal False_M1 : std_logic;
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signal False_M1 : std_logic;
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signal IntCycle_n : std_logic;
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signal IntCycle_n : std_logic;
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signal IORQ : std_logic;
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signal IORQ : std_logic;
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signal Write : std_logic;
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signal Write : std_logic;
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Line 99... |
signal MCycle : std_logic_vector(2 downto 0);
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signal MCycle : std_logic_vector(2 downto 0);
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signal TState : std_logic_vector(2 downto 0);
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signal TState : std_logic_vector(2 downto 0);
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|
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begin
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begin
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|
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CEN <= '1';
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|
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process (RESET_n, CLK_n)
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process (RESET_n, CLK_n)
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begin
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begin
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if RESET_n = '0' then
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if RESET_n = '0' then
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Reset_s <= '0';
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Reset_s <= '0';
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elsif CLK_n'event and CLK_n = '1' then
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elsif CLK_n'event and CLK_n = '1' then
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| Line 109... |
Line 114... |
|
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u0 : T80
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u0 : T80
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generic map(
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generic map(
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Mode => Mode)
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Mode => Mode)
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port map(
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port map(
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CEN => CEN,
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M1_n => M1_n,
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M1_n => M1_n,
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IORQ => IORQ,
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IORQ => IORQ,
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Write => Write,
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Write => Write,
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RFSH_n => RFSH_n,
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RFSH_n => RFSH_n,
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HALT_n => HALT_n,
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HALT_n => HALT_n,
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