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Line 1... |
--
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--
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-- Z80 compatible microprocessor core, asynchronous top level
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-- Z80 compatible microprocessor core, asynchronous top level
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--
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--
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-- Version : 0242
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-- Version : 0247
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--
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 54... |
Line 54... |
--
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--
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-- 0240 : Updated for T80 interface change
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-- 0240 : Updated for T80 interface change
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--
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--
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-- 0242 : Updated for T80 interface change
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-- 0242 : Updated for T80 interface change
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--
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--
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-- 0247 : Fixed bus req/ack cycle
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.T80_Pack.all;
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use work.T80_Pack.all;
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Line 98... |
signal Write : std_logic;
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signal Write : std_logic;
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signal MREQ : std_logic;
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signal MREQ : std_logic;
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signal MReq_Inhibit : std_logic;
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signal MReq_Inhibit : std_logic;
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signal Req_Inhibit : std_logic;
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signal Req_Inhibit : std_logic;
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signal RD : std_logic;
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signal RD : std_logic;
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signal WR_i : std_logic;
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signal MREQ_n_i : std_logic;
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signal IORQ_n_i : std_logic;
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signal RD_n_i : std_logic;
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signal WR_n_i : std_logic;
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signal RFSH_n_i : std_logic;
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signal BUSAK_n_i : std_logic;
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signal A_i : std_logic_vector(15 downto 0);
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signal DO : std_logic_vector(7 downto 0);
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signal DO : std_logic_vector(7 downto 0);
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signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
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signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
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signal Wait_s : std_logic;
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signal Wait_s : std_logic;
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signal MCycle : std_logic_vector(2 downto 0);
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signal MCycle : std_logic_vector(2 downto 0);
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signal TState : std_logic_vector(2 downto 0);
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signal TState : std_logic_vector(2 downto 0);
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begin
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begin
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CEN <= '1';
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CEN <= '1';
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BUSAK_n <= BUSAK_n_i;
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MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
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RD_n_i <= not RD or Req_Inhibit;
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MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
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IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
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RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
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WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
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RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
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A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
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D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
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process (RESET_n, CLK_n)
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process (RESET_n, CLK_n)
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begin
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begin
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if RESET_n = '0' then
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if RESET_n = '0' then
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Reset_s <= '0';
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Reset_s <= '0';
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elsif CLK_n'event and CLK_n = '1' then
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elsif CLK_n'event and CLK_n = '1' then
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Line 146... |
CEN => CEN,
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CEN => CEN,
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M1_n => M1_n,
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M1_n => M1_n,
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IORQ => IORQ,
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IORQ => IORQ,
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NoRead => NoRead,
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NoRead => NoRead,
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Write => Write,
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Write => Write,
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RFSH_n => RFSH_n,
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RFSH_n => RFSH_n_i,
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HALT_n => HALT_n,
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HALT_n => HALT_n,
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WAIT_n => Wait_s,
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WAIT_n => Wait_s,
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INT_n => INT_n,
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INT_n => INT_n,
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NMI_n => NMI_n,
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NMI_n => NMI_n,
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RESET_n => Reset_s,
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RESET_n => Reset_s,
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BUSRQ_n => BUSRQ_n,
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BUSRQ_n => BUSRQ_n,
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BUSAK_n => BUSAK_n,
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BUSAK_n => BUSAK_n_i,
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CLK_n => CLK_n,
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CLK_n => CLK_n,
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A => A,
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A => A_i,
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DInst => D,
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DInst => D,
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DI => DI_Reg,
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DI => DI_Reg,
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DO => DO,
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DO => DO,
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MC => MCycle,
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MC => MCycle,
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TS => TState,
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TS => TState,
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IntCycle_n => IntCycle_n);
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IntCycle_n => IntCycle_n);
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D <= DO when Write = '1' else (others => 'Z');
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process (CLK_n)
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process (CLK_n)
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begin
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begin
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if CLK_n'event and CLK_n = '0' then
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if CLK_n'event and CLK_n = '0' then
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WR_n <= WR_i;
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Wait_s <= WAIT_n;
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Wait_s <= WAIT_n;
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if TState = "011" then
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if TState = "011" and BUSAK_n_i = '1' then
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DI_Reg <= to_x01(D);
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DI_Reg <= to_x01(D);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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MREQ_n <= not MREQ or (Req_Inhibit and MReq_Inhibit);
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RD_n <= not RD or Req_Inhibit;
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process (Reset_s,CLK_n)
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process (Reset_s,CLK_n)
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begin
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begin
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if Reset_s = '0' then
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if Reset_s = '0' then
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WR_i <= '1';
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WR_n_i <= '1';
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elsif CLK_n'event and CLK_n = '1' then
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elsif CLK_n'event and CLK_n = '1' then
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WR_i <= '1';
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WR_n_i <= '1';
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if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
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if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
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WR_i <= not Write;
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WR_n_i <= not Write;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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process (Reset_s,CLK_n)
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process (Reset_s,CLK_n)
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Line 215... |
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process(Reset_s,CLK_n)
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process(Reset_s,CLK_n)
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begin
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begin
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if Reset_s = '0' then
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if Reset_s = '0' then
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RD <= '0';
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RD <= '0';
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IORQ_n <= '1';
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IORQ_n_i <= '1';
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MREQ <= '0';
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MREQ <= '0';
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elsif CLK_n'event and CLK_n = '0' then
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elsif CLK_n'event and CLK_n = '0' then
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if MCycle = "001" then
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if MCycle = "001" then
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if TState = "001" then
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if TState = "001" then
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RD <= IntCycle_n;
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RD <= IntCycle_n;
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MREQ <= IntCycle_n;
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MREQ <= IntCycle_n;
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IORQ_n <= IntCycle_n;
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IORQ_n_i <= IntCycle_n;
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end if;
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end if;
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if TState = "011" then
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if TState = "011" then
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RD <= '0';
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RD <= '0';
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IORQ_n <= '1';
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IORQ_n_i <= '1';
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MREQ <= '1';
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MREQ <= '1';
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end if;
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end if;
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if TState = "100" then
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if TState = "100" then
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MREQ <= '0';
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MREQ <= '0';
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end if;
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end if;
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else
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else
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if TState = "001" and NoRead = '0' then
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if TState = "001" and NoRead = '0' then
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RD <= not Write;
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RD <= not Write;
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IORQ_n <= not IORQ;
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IORQ_n_i <= not IORQ;
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MREQ <= not IORQ;
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MREQ <= not IORQ;
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end if;
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end if;
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if TState = "011" then
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if TState = "011" then
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RD <= '0';
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RD <= '0';
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IORQ_n <= '1';
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IORQ_n_i <= '1';
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MREQ <= '0';
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MREQ <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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