| Line 1... |
Line 1... |
--
|
--
|
-- Z80 compatible microprocessor core, synchronous top level
|
-- Z80 compatible microprocessor core, synchronous top level
|
-- Different timing than the original z80
|
-- Different timing than the original z80
|
-- Inputs needs to be synchronous and outputs may glitch
|
-- Inputs needs to be synchronous and outputs may glitch
|
--
|
--
|
-- Version : 0211
|
-- Version : 0235
|
--
|
--
|
-- Copyright (c) 2001-2002 Daniel Wallner (dwallner@hem2.passagen.se)
|
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
--
|
--
|
-- All rights reserved
|
-- All rights reserved
|
--
|
--
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- modification, are permitted provided that the following conditions are met:
|
-- modification, are permitted provided that the following conditions are met:
|
| Line 38... |
Line 38... |
-- Please report bugs to the author, but before you do so, please
|
-- Please report bugs to the author, but before you do so, please
|
-- make sure that this is not a derivative work and that
|
-- make sure that this is not a derivative work and that
|
-- you have the latest version of this file.
|
-- you have the latest version of this file.
|
--
|
--
|
-- The latest version of this file can be found at:
|
-- The latest version of this file can be found at:
|
-- http://hem.passagen.se/dwallner/vhdl.html
|
-- http://www.opencores.org/cvsweb.shtml/t80/
|
--
|
--
|
-- Limitations :
|
-- Limitations :
|
--
|
--
|
-- File history :
|
-- File history :
|
--
|
--
|
| Line 50... |
Line 50... |
--
|
--
|
-- 0210 : Fixed read with wait
|
-- 0210 : Fixed read with wait
|
--
|
--
|
-- 0211 : Fixed interrupt cycle
|
-- 0211 : Fixed interrupt cycle
|
--
|
--
|
|
-- 0235 : Updated for T80 interface change
|
|
--
|
|
|
library IEEE;
|
library IEEE;
|
use IEEE.std_logic_1164.all;
|
use IEEE.std_logic_1164.all;
|
use IEEE.numeric_std.all;
|
use IEEE.numeric_std.all;
|
use work.T80_Pack.all;
|
use work.T80_Pack.all;
|
| Line 83... |
Line 85... |
);
|
);
|
end T80s;
|
end T80s;
|
|
|
architecture rtl of T80s is
|
architecture rtl of T80s is
|
|
|
|
signal CEN : std_logic;
|
signal False_M1 : std_logic;
|
signal False_M1 : std_logic;
|
signal IntCycle_n : std_logic;
|
signal IntCycle_n : std_logic;
|
signal Write : std_logic;
|
signal Write : std_logic;
|
signal IORQ : std_logic;
|
signal IORQ : std_logic;
|
signal DI_Reg : std_logic_vector(7 downto 0);
|
signal DI_Reg : std_logic_vector(7 downto 0);
|
signal MCycle : std_logic_vector(2 downto 0);
|
signal MCycle : std_logic_vector(2 downto 0);
|
signal TState : std_logic_vector(2 downto 0);
|
signal TState : std_logic_vector(2 downto 0);
|
|
|
begin
|
begin
|
|
|
|
CEN <= '1';
|
|
|
u0 : T80
|
u0 : T80
|
generic map(
|
generic map(
|
Mode => Mode)
|
Mode => Mode)
|
port map(
|
port map(
|
|
CEN => CEN,
|
M1_n => M1_n,
|
M1_n => M1_n,
|
IORQ => IORQ,
|
IORQ => IORQ,
|
Write => Write,
|
Write => Write,
|
RFSH_n => RFSH_n,
|
RFSH_n => RFSH_n,
|
HALT_n => HALT_n,
|
HALT_n => HALT_n,
|
