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--
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--
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-- Z80 compatible microprocessor core, synchronous top level
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-- Z80 compatible microprocessor core, synchronous top level
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-- Different timing than the original z80
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-- Different timing than the original z80
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-- Inputs needs to be synchronous and outputs may glitch
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-- Inputs needs to be synchronous and outputs may glitch
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--
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--
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-- Version : 0235
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-- Version : 0236
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--
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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--
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--
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-- 0211 : Fixed interrupt cycle
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-- 0211 : Fixed interrupt cycle
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--
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--
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-- 0235 : Updated for T80 interface change
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-- 0235 : Updated for T80 interface change
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--
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--
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-- 0236 : Added T2Write generic
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.T80_Pack.all;
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use work.T80_Pack.all;
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entity T80s is
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entity T80s is
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generic(
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generic(
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Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
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);
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);
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port(
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port(
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RESET_n : in std_logic;
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RESET_n : in std_logic;
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CLK_n : in std_logic;
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CLK_n : in std_logic;
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WAIT_n : in std_logic;
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WAIT_n : in std_logic;
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if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '0' then
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if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '0' then
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RD_n <= '0';
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RD_n <= '0';
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IORQ_n <= not IORQ;
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IORQ_n <= not IORQ;
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MREQ_n <= IORQ;
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MREQ_n <= IORQ;
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end if;
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end if;
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if T2Write = 0 then
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if TState = "010" and Write = '1' then
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if TState = "010" and Write = '1' then
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WR_n <= '0';
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WR_n <= '0';
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IORQ_n <= not IORQ;
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IORQ_n <= not IORQ;
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MREQ_n <= IORQ;
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MREQ_n <= IORQ;
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end if;
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end if;
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else
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if TState = "001" and Write = '1' then
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WR_n <= '0';
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IORQ_n <= not IORQ;
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MREQ_n <= IORQ;
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end if;
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end if;
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end if;
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end if;
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if TState = "010" and Wait_n = '1' then
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if TState = "010" and Wait_n = '1' then
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DI_Reg <= DI;
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DI_Reg <= DI;
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end if;
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end if;
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end if;
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end if;
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