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Line 1... |
--
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--
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-- Z80 compatible microprocessor core, synchronous top level
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-- Z80 compatible microprocessor core, synchronous top level
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-- Different timing than the original z80
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-- Different timing than the original z80
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-- Inputs needs to be synchronous and outputs may glitch
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-- Inputs needs to be synchronous and outputs may glitch
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--
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--
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-- Version : 0238
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-- Version : 0240
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--
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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| Line 58... |
Line 58... |
--
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--
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-- 0237 : Fixed T2Write with wait state
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-- 0237 : Fixed T2Write with wait state
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--
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--
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-- 0238 : Updated for T80 interface change
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-- 0238 : Updated for T80 interface change
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--
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--
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-- 0240 : Updated for T80 interface change
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.T80_Pack.all;
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use work.T80_Pack.all;
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end T80s;
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end T80s;
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architecture rtl of T80s is
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architecture rtl of T80s is
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signal CEN : std_logic;
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signal CEN : std_logic;
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signal False_M1 : std_logic;
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signal IntCycle_n : std_logic;
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signal IntCycle_n : std_logic;
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signal NoRead : std_logic;
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signal NoRead : std_logic;
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signal Write : std_logic;
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signal Write : std_logic;
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signal IORQ : std_logic;
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signal IORQ : std_logic;
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signal DI_Reg : std_logic_vector(7 downto 0);
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signal DI_Reg : std_logic_vector(7 downto 0);
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DInst => DI,
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DInst => DI,
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DI => DI_Reg,
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DI => DI_Reg,
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DO => DO,
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DO => DO,
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MC => MCycle,
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MC => MCycle,
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TS => TState,
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TS => TState,
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False_M1 => False_M1,
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IntCycle_n => IntCycle_n);
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IntCycle_n => IntCycle_n);
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process (RESET_n, CLK_n)
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process (RESET_n, CLK_n)
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begin
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begin
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if RESET_n = '0' then
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if RESET_n = '0' then
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elsif CLK_n'event and CLK_n = '1' then
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elsif CLK_n'event and CLK_n = '1' then
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RD_n <= '1';
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RD_n <= '1';
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WR_n <= '1';
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WR_n <= '1';
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IORQ_n <= '1';
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IORQ_n <= '1';
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MREQ_n <= '1';
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MREQ_n <= '1';
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if MCycle = "001" and False_M1 = '0' then
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if MCycle = "001" then
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if TState = "001" or (TState = "010" and Wait_n = '0') then
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if TState = "001" or (TState = "010" and Wait_n = '0') then
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RD_n <= not IntCycle_n;
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RD_n <= not IntCycle_n;
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MREQ_n <= not IntCycle_n;
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MREQ_n <= not IntCycle_n;
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IORQ_n <= IntCycle_n;
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IORQ_n <= IntCycle_n;
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end if;
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end if;
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