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[/] [t80/] [trunk/] [rtl/] [vhdl/] [T80se.vhd] - Diff between revs 18 and 23
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| Rev 18 |
Rev 23 |
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--
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--
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-- Z80 compatible microprocessor core, synchronous top level with clock enable
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-- Z80 compatible microprocessor core, synchronous top level with clock enable
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-- Different timing than the original z80
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-- Different timing than the original z80
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-- Inputs needs to be synchronous and outputs may glitch
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-- Inputs needs to be synchronous and outputs may glitch
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--
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--
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-- Version : 0236
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-- Version : 0237
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--
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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Line 48... |
--
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--
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-- 0235 : First release
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-- 0235 : First release
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--
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--
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-- 0236 : Added T2Write generic
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-- 0236 : Added T2Write generic
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--
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--
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-- 0237 : Fixed T2Write with wait state
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.T80_Pack.all;
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use work.T80_Pack.all;
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WR_n <= '0';
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WR_n <= '0';
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IORQ_n <= not IORQ;
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IORQ_n <= not IORQ;
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MREQ_n <= IORQ;
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MREQ_n <= IORQ;
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end if;
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end if;
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else
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else
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if TState = "001" and Write = '1' then
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if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
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WR_n <= '0';
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WR_n <= '0';
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IORQ_n <= not IORQ;
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IORQ_n <= not IORQ;
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MREQ_n <= IORQ;
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MREQ_n <= IORQ;
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end if;
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end if;
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end if;
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end if;
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