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[/] [t80/] [trunk/] [rtl/] [vhdl/] [T80se.vhd] - Diff between revs 29 and 35
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Rev 35 |
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--
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--
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-- Z80 compatible microprocessor core, synchronous top level with clock enable
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-- Z80 compatible microprocessor core, synchronous top level with clock enable
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-- Different timing than the original z80
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-- Different timing than the original z80
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-- Inputs needs to be synchronous and outputs may glitch
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-- Inputs needs to be synchronous and outputs may glitch
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--
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--
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-- Version : 0240
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-- Version : 0242
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--
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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--
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--
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-- 0238 : Updated for T80 interface change
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-- 0238 : Updated for T80 interface change
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--
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--
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-- 0240 : Updated for T80 interface change
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-- 0240 : Updated for T80 interface change
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--
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--
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-- 0242 : Updated for T80 interface change
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.T80_Pack.all;
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use work.T80_Pack.all;
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entity T80se is
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entity T80se is
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generic(
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generic(
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Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
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T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
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IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
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);
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);
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port(
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port(
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RESET_n : in std_logic;
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RESET_n : in std_logic;
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CLK_n : in std_logic;
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CLK_n : in std_logic;
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CLKEN : in std_logic;
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CLKEN : in std_logic;
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begin
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begin
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u0 : T80
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u0 : T80
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generic map(
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generic map(
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Mode => Mode)
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Mode => Mode,
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IOWait => IOWait)
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port map(
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port map(
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CEN => CLKEN,
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CEN => CLKEN,
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M1_n => M1_n,
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M1_n => M1_n,
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IORQ => IORQ,
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IORQ => IORQ,
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NoRead => NoRead,
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NoRead => NoRead,
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