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[/] [tcp_socket/] [trunk/] [TCPIP.rst] - Diff between revs 3 and 4

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Chips-2.0 Demo for SP605 Development Card
Chips-2.0 Demo for Atlys Development Card
=========================================
=========================================
 
 
:Author: Jonathan P Dawson
:Author: Jonathan P Dawson
:Date: 2013-10-17
:Date: 2013-10-17
:email: chips@jondawson.org.uk
:email: chips@jondawson.org.uk
Line 105... Line 105...
 
 
 
 
Stream Interconnect Conventions
Stream Interconnect Conventions
===============================
===============================
 
 
The main aims of the interface are:
The interfaces are based on the Chips Physical Interface Convetions which are
 
described in the Chips-2.0 `reference manual
 
`_.
 
 
  - To be simple to implement.
 
  - Add little performance/logic overhead.
 
  - Allow designs to grow without adding extra levels of asynchronous logic.
 
  - Easy to interface with standard interconnects.
 
 
 
::
 
 
 
  RST >-o-----------------------------+
 
  CLK >-+-o-------------------------+ |
 
        | |                         | |
 
        | |   +-----------+         | |     +--------------+
 
        | |   | TX        |         | |     | RX           |
 
        | +--->           |         | +----->              |
 
        +----->           |         +------->              |
 
              |           |                 |              |
 
              |           |       |              |
 
              |       out >=================> in           |
 
              |           | _STB  |              |
 
              |       out >-----------------> in           |
 
              |           | _ACK  |              |
 
              |       in  <-----------------< out          |
 
              |           |                 |              |
 
              +-----------+                 +--------------+
 
 
 
Global Signals
 
--------------
 
 
 
 
 
 
 
+------+-----------+------+-------------+
 
| Name | Direction | Type | Description |
 
+------+-----------+------+-------------+
 
| CLK  |   input   | bit  |    Clock    |
 
+------+-----------+------+-------------+
 
| RST  |   input   | bit  |    Reset    |
 
+------+-----------+------+-------------+
 
 
 
 
 
 
 
Interconnect Signals
 
--------------------
 
 
 
 
 
 
 
+----------------+-----------+------+-----------------------------------------------------------+
 
|      Name      | Direction | Type |                        Description                        |
 
+----------------+-----------+------+-----------------------------------------------------------+
 
|      |  TX to RX | bus  |                        Payload Data                       |
 
+----------------+-----------+------+-----------------------------------------------------------+
 
| _STB |  TX to RX | bit  | '1' indicates that payload data is valid and TX is ready. |
 
+----------------+-----------+------+-----------------------------------------------------------+
 
| _ACK |  TX to RX | bit  |              '1' indicates that RX is ready.              |
 
+----------------+-----------+------+-----------------------------------------------------------+
 
 
 
 
 
 
 
Interconnect Bus Transaction
 
----------------------------
 
 
 
- Both transmitter and receiver shall be synchronised to the '0' -> '1' transition of CLK.
 
- If RST is set to '1' upon the '0' -> '1' transition of clock the transmitter shall terminate any active bus transaction and set _STB to '0'.
 
- If RST is set to '1' upon the '0' -> '1' transition of clock the receiver shall terminate any active bus transaction and set _ACK to '0'.
 
- If RST is set to '0', normal operation shall commence as follows:
 
- The transmitter may insert wait states on the bus by setting _STB '0'.
 
- The transmitter shall set _STB to '1' to signify that data is valid.
 
- Once _STB has been set to '1', it shall remain at '1' until the transaction completes.
 
- The transmitter shall ensure that  contains valid data for the entire period that _STB is '1'.
 
- The transmitter may set  to any value when _STB is '0'.
 
- The receiver may insert wait states on the bus by setting _ACK to '0'.
 
- The receiver shall set _ACK to '1' to signify that it is ready to receive data.
 
- Once _ACK has been set to '1', it shall remain at '1' until the transaction completes.
 
- Whenever _STB is '1' and _ACK are '1', a bus transaction shall complete on the following '0' -> '1' transition of CLK.
 
 
 
::
 
 
 
        RST
 
                         --------------------------------------------------------------
 
                           -   -   -   -   -   -   -   -   -   -   -   -   -   -   -
 
         CLK              | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
 
                         -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -
 
 
 
                         ----- ------- ------------------------------------------------
 
                    X VALID X
 
                         ----- ------- ------------------------------------------------
 
                               -------
 
        _STB        |       |
 
                         -----         ------------------------------------------------
 
                                   ---
 
        _ACK            |   |
 
                         ---------     ------------------------------------------------
 
 
 
 
 
                               ^^^^ RX adds wait states
 
 
 
                                   ^^^^  Data transfers
 
 
 
        RST
 
                         --------------------------------------------------------------
 
                           -   -   -   -   -   -   -   -   -   -   -   -   -   -   -
 
         CLK              | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
 
                         -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -
 
 
 
                         ----- ------- ------------------------------------------------
 
                    X VALID X
 
                         ----- ------- ------------------------------------------------
 
                                   ---
 
        _STB            |   |
 
                         ---------     ------------------------------------------------
 
                               -------
 
        _ACK        |       |
 
                         -----         ------------------------------------------------
 
 
 
 
 
                               ^^^^ TX adds wait states
 
 
 
                                   ^^^^  Data transfers
 
 
 
..
 
 
 
- Both the transmitter and receiver may commence a new transaction without inserting any wait states.
 
 
 
::
 
 
 
        RST
 
                         --------------------------------------------------------------
 
                           -   -   -   -   -   -   -   -   -   -   -   -   -   -   -
 
         CLK              | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
 
                         -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   -
 
 
 
                         ----- ------- ---- ---- --------------------------------------
 
                    X D0    X D1 X D2 X
 
                         ----- ------- ---- ---- --------------------------------------
 
                                   -------------
 
        _STB            |             |
 
                         ---------               --------------------------------------
 
                               -----------------
 
        _ACK        |                 |
 
                         -----                   --------------------------------------
 
 
 
                                ^^^^ TX adds wait states
 
 
 
                                     ^^^^  Data transfers
 
 
 
                                         ^^^^ STB and ACK needn't return to 0 between data words
 
 
 
..
 
 
 
 
 
- The receiver may delay a transaction by inserting wait states until the transmitter indicates that data is available.
 
 
 
- The transmitter shall not delay a transaction by inserting wait states until the receiver is ready to accept data.
 
 
 
- Deadlock would occur if both the transmitter and receiver delayed a transaction until the other was ready.
 

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