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Line 156... |
os.system("iverilog -o %s %s"%(self.name + "_tb", files))
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os.system("iverilog -o %s %s"%(self.name + "_tb", files))
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if run:
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if run:
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return os.system("vvp %s"%(self.name + "_tb"))
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return os.system("vvp %s"%(self.name + "_tb"))
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class Component:
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class Component:
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"""You can use the component class to add new components to your chip.
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"""You can use the component class to add new components to your chip.
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Components are written in C, and you need to supply the C code for the
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Components are written in C, and you need to supply the C code for the
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component when you create it. The Chips API will automatically compile the
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component when you create it. The Chips API will automatically compile the
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Line 190... |
Line 189... |
+ inputs, a list of *Wires* (or *Inputs*) to connect to the component inputs
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+ inputs, a list of *Wires* (or *Inputs*) to connect to the component inputs
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+ outputs, a list of *Wires* (or *Outputs*) to connect to the component outputs"""
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+ outputs, a list of *Wires* (or *Outputs*) to connect to the component outputs"""
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return _Instance(self, chip, inputs, outputs)
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return _Instance(self, chip, inputs, outputs)
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class VerilogComponent(Component):
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"""You can use the component class to add new components to your chip.
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This version of Component allows components to be written directly in verilog.
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my_component = Adder("adder", inputs = ["a", "b"], outputs = ["z"])
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Once you have defined a component you can use the __call__ method to create
|
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an instance of the component.
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"""
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def __init__(self, name, inputs, outputs, docs):
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"""Takes a single string argument, the C code to compile"""
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self.name = name
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self.inputs = inputs
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self.outputs = outputs
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self.docs = docs
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class _Instance:
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class _Instance:
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"""This class represents a component instance. You don't normaly need to
|
"""This class represents a component instance. You don't normaly need to
|
create them directly, use the Component.__call__ method."""
|
create them directly, use the Component.__call__ method."""
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