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[/] [test/] [trunk/] [wb_z80/] [rtl/] [memstate2.v] - Diff between revs 45 and 46

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//  In the former case, we throw out the instruction that arrives on the next tick, and restart the
//  In the former case, we throw out the instruction that arrives on the next tick, and restart the
//  instruction pipeline,   In the latter case, we simply wait a tick for the ir2 operaton to 
//  instruction pipeline,   In the latter case, we simply wait a tick for the ir2 operaton to 
//  complete before starting the ir1 operation  
//  complete before starting the ir1 operation  
//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
//
//
//  $Id: memstate2.v,v 1.1 2004-04-17 07:39:21 mihal Exp $
//  $Id: memstate2.v,v 1.2 2004-04-17 08:02:00 mihal Exp $
//
//
//  $Date: 2004-04-17 07:39:21 $
//  $Date: 2004-04-17 08:02:00 $
//  $Revision: 1.1 $
//  $Revision: 1.2 $
//  $Author: mihal $
//  $Author: mihal $
//  $Locker:  $
//  $Locker:  $
//  $State: Exp $
//  $State: Exp $
//
//
// Change History:
// Change History:
//      $Log: not supported by cvs2svn $
//      $Log: not supported by cvs2svn $
 
//      Revision 1.1  2004/04/17 07:39:21  mihal
 
//      testing lint
 
//
//      Revision 1.4  2004/04/16 18:16:57  bporcella
//      Revision 1.4  2004/04/16 18:16:57  bporcella
//      try lint
//      try lint
//
//
//      Revision 1.3  2004/04/16 17:06:54  bporcella
//      Revision 1.3  2004/04/16 17:06:54  bporcella
//      no code change  -  added a comment and test lint
//      no code change  -  added a comment and test lint
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//      Revision 1.1.1.1  2004/04/13 23:50:19  bporcella
//      Revision 1.1.1.1  2004/04/13 23:50:19  bporcella
//      import first files
//      import first files
//
//
//
//
//
//
 
//
//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0
//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0
 
 
module memstate2(wb_adr, wb_we, wb_cyc, wb_stb, wb_lock, wb_tga_io, wb_dat_o,  add_out,
module memstate2(wb_adr, wb_we, wb_cyc, wb_stb, wb_lock, wb_tga_io, wb_dat_o,  add_out,
                exec_ir2, ir1, ir2, ir1dd, ir1fd, ir2dd, ir2fd, nn, sp,
                exec_ir2, ir1, ir2, ir1dd, ir1fd, ir2dd, ir2fd, nn, sp,
 
 
                upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr,
                upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr,
                beq0, ceq0,
                beq0, ceq0,

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