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// In the former case, we throw out the instruction that arrives on the next tick, and restart the
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// In the former case, we throw out the instruction that arrives on the next tick, and restart the
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// instruction pipeline, In the latter case, we simply wait a tick for the ir2 operaton to
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// instruction pipeline, In the latter case, we simply wait a tick for the ir2 operaton to
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// complete before starting the ir1 operation
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// complete before starting the ir1 operation
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//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
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//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
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//
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//
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// $Id: memstate2.v,v 1.1 2004-04-17 07:39:21 mihal Exp $
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// $Id: memstate2.v,v 1.2 2004-04-17 08:02:00 mihal Exp $
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//
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//
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// $Date: 2004-04-17 07:39:21 $
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// $Date: 2004-04-17 08:02:00 $
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// $Revision: 1.1 $
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// $Revision: 1.2 $
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// $Author: mihal $
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// $Author: mihal $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2004/04/17 07:39:21 mihal
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// testing lint
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//
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// Revision 1.4 2004/04/16 18:16:57 bporcella
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// Revision 1.4 2004/04/16 18:16:57 bporcella
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// try lint
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// try lint
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//
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//
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// Revision 1.3 2004/04/16 17:06:54 bporcella
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// Revision 1.3 2004/04/16 17:06:54 bporcella
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// no code change - added a comment and test lint
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// no code change - added a comment and test lint
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// Revision 1.1.1.1 2004/04/13 23:50:19 bporcella
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// Revision 1.1.1.1 2004/04/13 23:50:19 bporcella
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// import first files
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// import first files
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//
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//
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//
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//
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//
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//
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//
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//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0
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//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0
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module memstate2(wb_adr, wb_we, wb_cyc, wb_stb, wb_lock, wb_tga_io, wb_dat_o, add_out,
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module memstate2(wb_adr, wb_we, wb_cyc, wb_stb, wb_lock, wb_tga_io, wb_dat_o, add_out,
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exec_ir2, ir1, ir2, ir1dd, ir1fd, ir2dd, ir2fd, nn, sp,
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exec_ir2, ir1, ir2, ir1dd, ir1fd, ir2dd, ir2fd, nn, sp,
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upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr,
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upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr,
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beq0, ceq0,
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beq0, ceq0,
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