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[/] [test_project/] [trunk/] [backend/] [sim_lib.v] - Diff between revs 16 and 22

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Line 9... Line 9...
module VCC
module VCC
  (
  (
   output Y
   output Y
   );
   );
   assign Y = 1'b1;
   assign Y = 1'b1;
endmodule; // VCC
endmodule // VCC
`timescale 1 ns / 100 ps
`timescale 1 ns / 100 ps
module CLKDLY
module CLKDLY
  (
  (
   output GL,
   output GL,
   input CLK, DLYGL0, DLYGL1, DLYGL2,DLYGL3,DLYGL4
   input CLK, DLYGL0, DLYGL1, DLYGL2,DLYGL3,DLYGL4

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