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Line 4... |
//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// ORPSoC Testbench file ////
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//// ORPSoC Testbench file ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// Somehow allow tracing to begin later in the sim ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Jeremy Bennett jeremy.bennett@embecosm.com ////
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//// - Jeremy Bennett jeremy.bennett@embecosm.com ////
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//// - Julius Baxter jb@orsoc.se ////
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//// - Julius Baxter jb@orsoc.se ////
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Line 52... |
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int sc_main (int argc,
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int sc_main (int argc,
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char *argv[] )
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char *argv[] )
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{
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{
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// CPU clock (also used as JTAG TCK) and reset (both active high and low)
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// CPU clock (also used as JTAG TCK) and reset (both active high and low)
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sc_time clkPeriod (BENCH_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
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sc_time clkPeriod (BENCH_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
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sc_clock clk ("clk", clkPeriod);
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sc_clock clk ("clk", clkPeriod);
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sc_signal<bool> rst;
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sc_signal<bool> rst;
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| Line 93... |
Line 95... |
Or1200MonitorSC *monitor; // Handle l.nop x instructions
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Or1200MonitorSC *monitor; // Handle l.nop x instructions
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UartSC *uart; // Handle UART signals
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UartSC *uart; // Handle UART signals
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// Instantiate the Verilator model, VCD trace handler and accessor
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// Instantiate the Verilator model, VCD trace handler and accessor
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orpsoc = new Vorpsoc_top ("orpsoc");
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orpsoc = new Vorpsoc_top ("orpsoc");
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trace = new TraceSC ("trace", orpsoc, "v-dump.vcd");
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trace = new TraceSC ("trace", orpsoc, argc, argv);
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accessor = new OrpsocAccess (orpsoc);
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accessor = new OrpsocAccess (orpsoc);
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// Instantiate the SystemC modules
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// Instantiate the SystemC modules
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reset = new ResetSC ("reset", BENCH_RESET_TIME);
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reset = new ResetSC ("reset", BENCH_RESET_TIME);
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monitor = new Or1200MonitorSC ("monitor", accessor);
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monitor = new Or1200MonitorSC ("monitor", accessor);
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