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[/] [test_project/] [trunk/] [bench/] [verilog/] [or1200_monitor.v] - Diff between revs 34 and 39

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Rev 34 Rev 39
Line 103... Line 103...
`define OR1200_TOP orpsoc_testbench.dut.i_or1k.i_or1200_top
`define OR1200_TOP orpsoc_testbench.dut.i_or1k.i_or1200_top
 
 
//
//
// Enable display_arch_state task
// Enable display_arch_state task
//
//
`define OR1200_DISPLAY_ARCH_STATE
//`define OR1200_DISPLAY_ARCH_STATE
 
 
module or1200_monitor;
module or1200_monitor;
 
 
   integer fexe;
   integer fexe;
   reg [23:0] ref;
   reg [23:0] ref;

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